1/* 2 * Device Tree Source for AMCC Glacier (460GT) 3 * 4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <1>; 14 model = "amcc,glacier"; 15 compatible = "amcc,glacier", "amcc,canyonlands"; 16 dcr-parent = <&/cpus/cpu@0>; 17 18 aliases { 19 ethernet0 = &EMAC0; 20 ethernet1 = &EMAC1; 21 ethernet2 = &EMAC2; 22 ethernet3 = &EMAC3; 23 serial0 = &UART0; 24 serial1 = &UART1; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC,460GT"; 34 reg = <0>; 35 clock-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */ 37 i-cache-line-size = <20>; 38 d-cache-line-size = <20>; 39 i-cache-size = <8000>; 40 d-cache-size = <8000>; 41 dcr-controller; 42 dcr-access-method = "native"; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0 0 0>; /* Filled in by U-Boot */ 49 }; 50 51 UIC0: interrupt-controller0 { 52 compatible = "ibm,uic-460gt","ibm,uic"; 53 interrupt-controller; 54 cell-index = <0>; 55 dcr-reg = <0c0 009>; 56 #address-cells = <0>; 57 #size-cells = <0>; 58 #interrupt-cells = <2>; 59 }; 60 61 UIC1: interrupt-controller1 { 62 compatible = "ibm,uic-460gt","ibm,uic"; 63 interrupt-controller; 64 cell-index = <1>; 65 dcr-reg = <0d0 009>; 66 #address-cells = <0>; 67 #size-cells = <0>; 68 #interrupt-cells = <2>; 69 interrupts = <1e 4 1f 4>; /* cascade */ 70 interrupt-parent = <&UIC0>; 71 }; 72 73 UIC2: interrupt-controller2 { 74 compatible = "ibm,uic-460gt","ibm,uic"; 75 interrupt-controller; 76 cell-index = <2>; 77 dcr-reg = <0e0 009>; 78 #address-cells = <0>; 79 #size-cells = <0>; 80 #interrupt-cells = <2>; 81 interrupts = <a 4 b 4>; /* cascade */ 82 interrupt-parent = <&UIC0>; 83 }; 84 85 UIC3: interrupt-controller3 { 86 compatible = "ibm,uic-460gt","ibm,uic"; 87 interrupt-controller; 88 cell-index = <3>; 89 dcr-reg = <0f0 009>; 90 #address-cells = <0>; 91 #size-cells = <0>; 92 #interrupt-cells = <2>; 93 interrupts = <10 4 11 4>; /* cascade */ 94 interrupt-parent = <&UIC0>; 95 }; 96 97 SDR0: sdr { 98 compatible = "ibm,sdr-460gt"; 99 dcr-reg = <00e 002>; 100 }; 101 102 CPR0: cpr { 103 compatible = "ibm,cpr-460gt"; 104 dcr-reg = <00c 002>; 105 }; 106 107 plb { 108 compatible = "ibm,plb-460gt", "ibm,plb4"; 109 #address-cells = <2>; 110 #size-cells = <1>; 111 ranges; 112 clock-frequency = <0>; /* Filled in by U-Boot */ 113 114 SDRAM0: sdram { 115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 116 dcr-reg = <010 2>; 117 }; 118 119 MAL0: mcmal { 120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 121 dcr-reg = <180 62>; 122 num-tx-chans = <4>; 123 num-rx-chans = <20>; 124 #address-cells = <0>; 125 #size-cells = <0>; 126 interrupt-parent = <&UIC2>; 127 interrupts = < /*TXEOB*/ 6 4 128 /*RXEOB*/ 7 4 129 /*SERR*/ 3 4 130 /*TXDE*/ 4 4 131 /*RXDE*/ 5 4>; 132 desc-base-addr-high = <8>; 133 }; 134 135 POB0: opb { 136 compatible = "ibm,opb-460gt", "ibm,opb"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <b0000000 4 b0000000 50000000>; 140 clock-frequency = <0>; /* Filled in by U-Boot */ 141 142 EBC0: ebc { 143 compatible = "ibm,ebc-460gt", "ibm,ebc"; 144 dcr-reg = <012 2>; 145 #address-cells = <2>; 146 #size-cells = <1>; 147 clock-frequency = <0>; /* Filled in by U-Boot */ 148 interrupts = <6 4>; 149 interrupt-parent = <&UIC1>; 150 }; 151 152 UART0: serial@ef600300 { 153 device_type = "serial"; 154 compatible = "ns16550"; 155 reg = <ef600300 8>; 156 virtual-reg = <ef600300>; 157 clock-frequency = <0>; /* Filled in by U-Boot */ 158 current-speed = <0>; /* Filled in by U-Boot */ 159 interrupt-parent = <&UIC1>; 160 interrupts = <1 4>; 161 }; 162 163 UART1: serial@ef600400 { 164 device_type = "serial"; 165 compatible = "ns16550"; 166 reg = <ef600400 8>; 167 virtual-reg = <ef600400>; 168 clock-frequency = <0>; /* Filled in by U-Boot */ 169 current-speed = <0>; /* Filled in by U-Boot */ 170 interrupt-parent = <&UIC0>; 171 interrupts = <1 4>; 172 }; 173 174 UART2: serial@ef600500 { 175 device_type = "serial"; 176 compatible = "ns16550"; 177 reg = <ef600500 8>; 178 virtual-reg = <ef600500>; 179 clock-frequency = <0>; /* Filled in by U-Boot */ 180 current-speed = <0>; /* Filled in by U-Boot */ 181 interrupt-parent = <&UIC1>; 182 interrupts = <1d 4>; 183 }; 184 185 UART3: serial@ef600600 { 186 device_type = "serial"; 187 compatible = "ns16550"; 188 reg = <ef600600 8>; 189 virtual-reg = <ef600600>; 190 clock-frequency = <0>; /* Filled in by U-Boot */ 191 current-speed = <0>; /* Filled in by U-Boot */ 192 interrupt-parent = <&UIC1>; 193 interrupts = <1e 4>; 194 }; 195 196 IIC0: i2c@ef600700 { 197 compatible = "ibm,iic-460gt", "ibm,iic"; 198 reg = <ef600700 14>; 199 interrupt-parent = <&UIC0>; 200 interrupts = <2 4>; 201 }; 202 203 IIC1: i2c@ef600800 { 204 compatible = "ibm,iic-460gt", "ibm,iic"; 205 reg = <ef600800 14>; 206 interrupt-parent = <&UIC0>; 207 interrupts = <3 4>; 208 }; 209 210 ZMII0: emac-zmii@ef600d00 { 211 compatible = "ibm,zmii-460gt", "ibm,zmii"; 212 reg = <ef600d00 c>; 213 }; 214 215 RGMII0: emac-rgmii@ef601500 { 216 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 217 reg = <ef601500 8>; 218 has-mdio; 219 }; 220 221 RGMII1: emac-rgmii@ef601600 { 222 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 223 reg = <ef601600 8>; 224 has-mdio; 225 }; 226 227 TAH0: emac-tah@ef601350 { 228 compatible = "ibm,tah-460gt", "ibm,tah"; 229 reg = <ef601350 30>; 230 }; 231 232 TAH1: emac-tah@ef601450 { 233 compatible = "ibm,tah-460gt", "ibm,tah"; 234 reg = <ef601450 30>; 235 }; 236 237 EMAC0: ethernet@ef600e00 { 238 device_type = "network"; 239 compatible = "ibm,emac-460gt", "ibm,emac4"; 240 interrupt-parent = <&EMAC0>; 241 interrupts = <0 1>; 242 #interrupt-cells = <1>; 243 #address-cells = <0>; 244 #size-cells = <0>; 245 interrupt-map = </*Status*/ 0 &UIC2 10 4 246 /*Wake*/ 1 &UIC2 14 4>; 247 reg = <ef600e00 70>; 248 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 249 mal-device = <&MAL0>; 250 mal-tx-channel = <0>; 251 mal-rx-channel = <0>; 252 cell-index = <0>; 253 max-frame-size = <2328>; 254 rx-fifo-size = <1000>; 255 tx-fifo-size = <800>; 256 phy-mode = "rgmii"; 257 phy-map = <00000000>; 258 rgmii-device = <&RGMII0>; 259 rgmii-channel = <0>; 260 tah-device = <&TAH0>; 261 tah-channel = <0>; 262 has-inverted-stacr-oc; 263 has-new-stacr-staopc; 264 }; 265 266 EMAC1: ethernet@ef600f00 { 267 device_type = "network"; 268 compatible = "ibm,emac-460gt", "ibm,emac4"; 269 interrupt-parent = <&EMAC1>; 270 interrupts = <0 1>; 271 #interrupt-cells = <1>; 272 #address-cells = <0>; 273 #size-cells = <0>; 274 interrupt-map = </*Status*/ 0 &UIC2 11 4 275 /*Wake*/ 1 &UIC2 15 4>; 276 reg = <ef600f00 70>; 277 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 278 mal-device = <&MAL0>; 279 mal-tx-channel = <1>; 280 mal-rx-channel = <8>; 281 cell-index = <1>; 282 max-frame-size = <2328>; 283 rx-fifo-size = <1000>; 284 tx-fifo-size = <800>; 285 phy-mode = "rgmii"; 286 phy-map = <00000000>; 287 rgmii-device = <&RGMII0>; 288 rgmii-channel = <1>; 289 tah-device = <&TAH1>; 290 tah-channel = <1>; 291 has-inverted-stacr-oc; 292 has-new-stacr-staopc; 293 mdio-device = <&EMAC0>; 294 }; 295 296 EMAC2: ethernet@ef601100 { 297 device_type = "network"; 298 compatible = "ibm,emac-460gt", "ibm,emac4"; 299 interrupt-parent = <&EMAC2>; 300 interrupts = <0 1>; 301 #interrupt-cells = <1>; 302 #address-cells = <0>; 303 #size-cells = <0>; 304 interrupt-map = </*Status*/ 0 &UIC2 12 4 305 /*Wake*/ 1 &UIC2 16 4>; 306 reg = <ef601100 70>; 307 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 308 mal-device = <&MAL0>; 309 mal-tx-channel = <2>; 310 mal-rx-channel = <10>; 311 cell-index = <2>; 312 max-frame-size = <2328>; 313 rx-fifo-size = <1000>; 314 tx-fifo-size = <800>; 315 phy-mode = "rgmii"; 316 phy-map = <00000000>; 317 rgmii-device = <&RGMII1>; 318 rgmii-channel = <0>; 319 has-inverted-stacr-oc; 320 has-new-stacr-staopc; 321 mdio-device = <&EMAC0>; 322 }; 323 324 EMAC3: ethernet@ef601200 { 325 device_type = "network"; 326 compatible = "ibm,emac-460gt", "ibm,emac4"; 327 interrupt-parent = <&EMAC3>; 328 interrupts = <0 1>; 329 #interrupt-cells = <1>; 330 #address-cells = <0>; 331 #size-cells = <0>; 332 interrupt-map = </*Status*/ 0 &UIC2 13 4 333 /*Wake*/ 1 &UIC2 17 4>; 334 reg = <ef601200 70>; 335 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 336 mal-device = <&MAL0>; 337 mal-tx-channel = <3>; 338 mal-rx-channel = <18>; 339 cell-index = <3>; 340 max-frame-size = <2328>; 341 rx-fifo-size = <1000>; 342 tx-fifo-size = <800>; 343 phy-mode = "rgmii"; 344 phy-map = <00000000>; 345 rgmii-device = <&RGMII1>; 346 rgmii-channel = <1>; 347 has-inverted-stacr-oc; 348 has-new-stacr-staopc; 349 mdio-device = <&EMAC0>; 350 }; 351 }; 352 353 PCIX0: pci@c0ec00000 { 354 device_type = "pci"; 355 #interrupt-cells = <1>; 356 #size-cells = <2>; 357 #address-cells = <3>; 358 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 359 primary; 360 large-inbound-windows; 361 enable-msi-hole; 362 reg = <c 0ec00000 8 /* Config space access */ 363 0 0 0 /* no IACK cycles */ 364 c 0ed00000 4 /* Special cycles */ 365 c 0ec80000 100 /* Internal registers */ 366 c 0ec80100 fc>; /* Internal messaging registers */ 367 368 /* Outbound ranges, one memory and one IO, 369 * later cannot be changed 370 */ 371 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 372 01000000 0 00000000 0000000c 08000000 0 00010000>; 373 374 /* Inbound 2GB range starting at 0 */ 375 dma-ranges = <42000000 0 0 0 0 0 80000000>; 376 377 /* This drives busses 0 to 0x3f */ 378 bus-range = <0 3f>; 379 380 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 381 interrupt-map-mask = <0000 0 0 0>; 382 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 383 }; 384 385 PCIE0: pciex@d00000000 { 386 device_type = "pci"; 387 #interrupt-cells = <1>; 388 #size-cells = <2>; 389 #address-cells = <3>; 390 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 391 primary; 392 port = <0>; /* port number */ 393 reg = <d 00000000 20000000 /* Config space access */ 394 c 08010000 00001000>; /* Registers */ 395 dcr-reg = <100 020>; 396 sdr-base = <300>; 397 398 /* Outbound ranges, one memory and one IO, 399 * later cannot be changed 400 */ 401 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 402 01000000 0 00000000 0000000f 80000000 0 00010000>; 403 404 /* Inbound 2GB range starting at 0 */ 405 dma-ranges = <42000000 0 0 0 0 0 80000000>; 406 407 /* This drives busses 40 to 0x7f */ 408 bus-range = <40 7f>; 409 410 /* Legacy interrupts (note the weird polarity, the bridge seems 411 * to invert PCIe legacy interrupts). 412 * We are de-swizzling here because the numbers are actually for 413 * port of the root complex virtual P2P bridge. But I want 414 * to avoid putting a node for it in the tree, so the numbers 415 * below are basically de-swizzled numbers. 416 * The real slot is on idsel 0, so the swizzling is 1:1 417 */ 418 interrupt-map-mask = <0000 0 0 7>; 419 interrupt-map = < 420 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 421 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 422 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 423 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 424 }; 425 426 PCIE1: pciex@d20000000 { 427 device_type = "pci"; 428 #interrupt-cells = <1>; 429 #size-cells = <2>; 430 #address-cells = <3>; 431 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 432 primary; 433 port = <1>; /* port number */ 434 reg = <d 20000000 20000000 /* Config space access */ 435 c 08011000 00001000>; /* Registers */ 436 dcr-reg = <120 020>; 437 sdr-base = <340>; 438 439 /* Outbound ranges, one memory and one IO, 440 * later cannot be changed 441 */ 442 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 443 01000000 0 00000000 0000000f 80010000 0 00010000>; 444 445 /* Inbound 2GB range starting at 0 */ 446 dma-ranges = <42000000 0 0 0 0 0 80000000>; 447 448 /* This drives busses 80 to 0xbf */ 449 bus-range = <80 bf>; 450 451 /* Legacy interrupts (note the weird polarity, the bridge seems 452 * to invert PCIe legacy interrupts). 453 * We are de-swizzling here because the numbers are actually for 454 * port of the root complex virtual P2P bridge. But I want 455 * to avoid putting a node for it in the tree, so the numbers 456 * below are basically de-swizzled numbers. 457 * The real slot is on idsel 0, so the swizzling is 1:1 458 */ 459 interrupt-map-mask = <0000 0 0 7>; 460 interrupt-map = < 461 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 462 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 463 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 464 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 465 }; 466 }; 467}; 468