1/* 2 * Device Tree Source for AMCC Glacier (460GT) 3 * 4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <1>; 16 model = "amcc,glacier"; 17 compatible = "amcc,glacier", "amcc,canyonlands"; 18 dcr-parent = <&{/cpus/cpu@0}>; 19 20 aliases { 21 ethernet0 = &EMAC0; 22 ethernet1 = &EMAC1; 23 ethernet2 = &EMAC2; 24 ethernet3 = &EMAC3; 25 serial0 = &UART0; 26 serial1 = &UART1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 model = "PowerPC,460GT"; 36 reg = <0x00000000>; 37 clock-frequency = <0>; /* Filled in by U-Boot */ 38 timebase-frequency = <0>; /* Filled in by U-Boot */ 39 i-cache-line-size = <32>; 40 d-cache-line-size = <32>; 41 i-cache-size = <32768>; 42 d-cache-size = <32768>; 43 dcr-controller; 44 dcr-access-method = "native"; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 51 }; 52 53 UIC0: interrupt-controller0 { 54 compatible = "ibm,uic-460gt","ibm,uic"; 55 interrupt-controller; 56 cell-index = <0>; 57 dcr-reg = <0x0c0 0x009>; 58 #address-cells = <0>; 59 #size-cells = <0>; 60 #interrupt-cells = <2>; 61 }; 62 63 UIC1: interrupt-controller1 { 64 compatible = "ibm,uic-460gt","ibm,uic"; 65 interrupt-controller; 66 cell-index = <1>; 67 dcr-reg = <0x0d0 0x009>; 68 #address-cells = <0>; 69 #size-cells = <0>; 70 #interrupt-cells = <2>; 71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 72 interrupt-parent = <&UIC0>; 73 }; 74 75 UIC2: interrupt-controller2 { 76 compatible = "ibm,uic-460gt","ibm,uic"; 77 interrupt-controller; 78 cell-index = <2>; 79 dcr-reg = <0x0e0 0x009>; 80 #address-cells = <0>; 81 #size-cells = <0>; 82 #interrupt-cells = <2>; 83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 84 interrupt-parent = <&UIC0>; 85 }; 86 87 UIC3: interrupt-controller3 { 88 compatible = "ibm,uic-460gt","ibm,uic"; 89 interrupt-controller; 90 cell-index = <3>; 91 dcr-reg = <0x0f0 0x009>; 92 #address-cells = <0>; 93 #size-cells = <0>; 94 #interrupt-cells = <2>; 95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 96 interrupt-parent = <&UIC0>; 97 }; 98 99 SDR0: sdr { 100 compatible = "ibm,sdr-460gt"; 101 dcr-reg = <0x00e 0x002>; 102 }; 103 104 CPR0: cpr { 105 compatible = "ibm,cpr-460gt"; 106 dcr-reg = <0x00c 0x002>; 107 }; 108 109 plb { 110 compatible = "ibm,plb-460gt", "ibm,plb4"; 111 #address-cells = <2>; 112 #size-cells = <1>; 113 ranges; 114 clock-frequency = <0>; /* Filled in by U-Boot */ 115 116 SDRAM0: sdram { 117 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 118 dcr-reg = <0x010 0x002>; 119 }; 120 121 MAL0: mcmal { 122 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 123 dcr-reg = <0x180 0x062>; 124 num-tx-chans = <4>; 125 num-rx-chans = <32>; 126 #address-cells = <0>; 127 #size-cells = <0>; 128 interrupt-parent = <&UIC2>; 129 interrupts = < /*TXEOB*/ 0x6 0x4 130 /*RXEOB*/ 0x7 0x4 131 /*SERR*/ 0x3 0x4 132 /*TXDE*/ 0x4 0x4 133 /*RXDE*/ 0x5 0x4>; 134 desc-base-addr-high = <0x8>; 135 }; 136 137 POB0: opb { 138 compatible = "ibm,opb-460gt", "ibm,opb"; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 142 clock-frequency = <0>; /* Filled in by U-Boot */ 143 144 EBC0: ebc { 145 compatible = "ibm,ebc-460gt", "ibm,ebc"; 146 dcr-reg = <0x012 0x002>; 147 #address-cells = <2>; 148 #size-cells = <1>; 149 clock-frequency = <0>; /* Filled in by U-Boot */ 150 /* ranges property is supplied by U-Boot */ 151 interrupts = <0x6 0x4>; 152 interrupt-parent = <&UIC1>; 153 154 nor_flash@0,0 { 155 compatible = "amd,s29gl512n", "cfi-flash"; 156 bank-width = <2>; 157 reg = <0x00000000 0x00000000 0x04000000>; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 partition@0 { 161 label = "kernel"; 162 reg = <0x00000000 0x001e0000>; 163 }; 164 partition@1e0000 { 165 label = "dtb"; 166 reg = <0x001e0000 0x00020000>; 167 }; 168 partition@200000 { 169 label = "ramdisk"; 170 reg = <0x00200000 0x01400000>; 171 }; 172 partition@1600000 { 173 label = "jffs2"; 174 reg = <0x01600000 0x00400000>; 175 }; 176 partition@1a00000 { 177 label = "user"; 178 reg = <0x01a00000 0x02560000>; 179 }; 180 partition@3f60000 { 181 label = "env"; 182 reg = <0x03f60000 0x00040000>; 183 }; 184 partition@3fa0000 { 185 label = "u-boot"; 186 reg = <0x03fa0000 0x00060000>; 187 }; 188 }; 189 }; 190 191 UART0: serial@ef600300 { 192 device_type = "serial"; 193 compatible = "ns16550"; 194 reg = <0xef600300 0x00000008>; 195 virtual-reg = <0xef600300>; 196 clock-frequency = <0>; /* Filled in by U-Boot */ 197 current-speed = <0>; /* Filled in by U-Boot */ 198 interrupt-parent = <&UIC1>; 199 interrupts = <0x1 0x4>; 200 }; 201 202 UART1: serial@ef600400 { 203 device_type = "serial"; 204 compatible = "ns16550"; 205 reg = <0xef600400 0x00000008>; 206 virtual-reg = <0xef600400>; 207 clock-frequency = <0>; /* Filled in by U-Boot */ 208 current-speed = <0>; /* Filled in by U-Boot */ 209 interrupt-parent = <&UIC0>; 210 interrupts = <0x1 0x4>; 211 }; 212 213 UART2: serial@ef600500 { 214 device_type = "serial"; 215 compatible = "ns16550"; 216 reg = <0xef600500 0x00000008>; 217 virtual-reg = <0xef600500>; 218 clock-frequency = <0>; /* Filled in by U-Boot */ 219 current-speed = <0>; /* Filled in by U-Boot */ 220 interrupt-parent = <&UIC1>; 221 interrupts = <0x1d 0x4>; 222 }; 223 224 UART3: serial@ef600600 { 225 device_type = "serial"; 226 compatible = "ns16550"; 227 reg = <0xef600600 0x00000008>; 228 virtual-reg = <0xef600600>; 229 clock-frequency = <0>; /* Filled in by U-Boot */ 230 current-speed = <0>; /* Filled in by U-Boot */ 231 interrupt-parent = <&UIC1>; 232 interrupts = <0x1e 0x4>; 233 }; 234 235 IIC0: i2c@ef600700 { 236 compatible = "ibm,iic-460gt", "ibm,iic"; 237 reg = <0xef600700 0x00000014>; 238 interrupt-parent = <&UIC0>; 239 interrupts = <0x2 0x4>; 240 }; 241 242 IIC1: i2c@ef600800 { 243 compatible = "ibm,iic-460gt", "ibm,iic"; 244 reg = <0xef600800 0x00000014>; 245 interrupt-parent = <&UIC0>; 246 interrupts = <0x3 0x4>; 247 }; 248 249 ZMII0: emac-zmii@ef600d00 { 250 compatible = "ibm,zmii-460gt", "ibm,zmii"; 251 reg = <0xef600d00 0x0000000c>; 252 }; 253 254 RGMII0: emac-rgmii@ef601500 { 255 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 256 reg = <0xef601500 0x00000008>; 257 has-mdio; 258 }; 259 260 RGMII1: emac-rgmii@ef601600 { 261 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 262 reg = <0xef601600 0x00000008>; 263 has-mdio; 264 }; 265 266 TAH0: emac-tah@ef601350 { 267 compatible = "ibm,tah-460gt", "ibm,tah"; 268 reg = <0xef601350 0x00000030>; 269 }; 270 271 TAH1: emac-tah@ef601450 { 272 compatible = "ibm,tah-460gt", "ibm,tah"; 273 reg = <0xef601450 0x00000030>; 274 }; 275 276 EMAC0: ethernet@ef600e00 { 277 device_type = "network"; 278 compatible = "ibm,emac-460gt", "ibm,emac4"; 279 interrupt-parent = <&EMAC0>; 280 interrupts = <0x0 0x1>; 281 #interrupt-cells = <1>; 282 #address-cells = <0>; 283 #size-cells = <0>; 284 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 285 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 286 reg = <0xef600e00 0x00000074>; 287 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 288 mal-device = <&MAL0>; 289 mal-tx-channel = <0>; 290 mal-rx-channel = <0>; 291 cell-index = <0>; 292 max-frame-size = <9000>; 293 rx-fifo-size = <4096>; 294 tx-fifo-size = <2048>; 295 phy-mode = "rgmii"; 296 phy-map = <0x00000000>; 297 rgmii-device = <&RGMII0>; 298 rgmii-channel = <0>; 299 tah-device = <&TAH0>; 300 tah-channel = <0>; 301 has-inverted-stacr-oc; 302 has-new-stacr-staopc; 303 }; 304 305 EMAC1: ethernet@ef600f00 { 306 device_type = "network"; 307 compatible = "ibm,emac-460gt", "ibm,emac4"; 308 interrupt-parent = <&EMAC1>; 309 interrupts = <0x0 0x1>; 310 #interrupt-cells = <1>; 311 #address-cells = <0>; 312 #size-cells = <0>; 313 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 314 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 315 reg = <0xef600f00 0x00000074>; 316 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 317 mal-device = <&MAL0>; 318 mal-tx-channel = <1>; 319 mal-rx-channel = <8>; 320 cell-index = <1>; 321 max-frame-size = <9000>; 322 rx-fifo-size = <4096>; 323 tx-fifo-size = <2048>; 324 phy-mode = "rgmii"; 325 phy-map = <0x00000000>; 326 rgmii-device = <&RGMII0>; 327 rgmii-channel = <1>; 328 tah-device = <&TAH1>; 329 tah-channel = <1>; 330 has-inverted-stacr-oc; 331 has-new-stacr-staopc; 332 mdio-device = <&EMAC0>; 333 }; 334 335 EMAC2: ethernet@ef601100 { 336 device_type = "network"; 337 compatible = "ibm,emac-460gt", "ibm,emac4"; 338 interrupt-parent = <&EMAC2>; 339 interrupts = <0x0 0x1>; 340 #interrupt-cells = <1>; 341 #address-cells = <0>; 342 #size-cells = <0>; 343 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 344 /*Wake*/ 0x1 &UIC2 0x16 0x4>; 345 reg = <0xef601100 0x00000074>; 346 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 347 mal-device = <&MAL0>; 348 mal-tx-channel = <2>; 349 mal-rx-channel = <16>; 350 cell-index = <2>; 351 max-frame-size = <9000>; 352 rx-fifo-size = <4096>; 353 tx-fifo-size = <2048>; 354 phy-mode = "rgmii"; 355 phy-map = <0x00000000>; 356 rgmii-device = <&RGMII1>; 357 rgmii-channel = <0>; 358 has-inverted-stacr-oc; 359 has-new-stacr-staopc; 360 mdio-device = <&EMAC0>; 361 }; 362 363 EMAC3: ethernet@ef601200 { 364 device_type = "network"; 365 compatible = "ibm,emac-460gt", "ibm,emac4"; 366 interrupt-parent = <&EMAC3>; 367 interrupts = <0x0 0x1>; 368 #interrupt-cells = <1>; 369 #address-cells = <0>; 370 #size-cells = <0>; 371 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 372 /*Wake*/ 0x1 &UIC2 0x17 0x4>; 373 reg = <0xef601200 0x00000074>; 374 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 375 mal-device = <&MAL0>; 376 mal-tx-channel = <3>; 377 mal-rx-channel = <24>; 378 cell-index = <3>; 379 max-frame-size = <9000>; 380 rx-fifo-size = <4096>; 381 tx-fifo-size = <2048>; 382 phy-mode = "rgmii"; 383 phy-map = <0x00000000>; 384 rgmii-device = <&RGMII1>; 385 rgmii-channel = <1>; 386 has-inverted-stacr-oc; 387 has-new-stacr-staopc; 388 mdio-device = <&EMAC0>; 389 }; 390 }; 391 392 PCIX0: pci@c0ec00000 { 393 device_type = "pci"; 394 #interrupt-cells = <1>; 395 #size-cells = <2>; 396 #address-cells = <3>; 397 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; 398 primary; 399 large-inbound-windows; 400 enable-msi-hole; 401 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 402 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 403 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 404 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 405 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 406 407 /* Outbound ranges, one memory and one IO, 408 * later cannot be changed 409 */ 410 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 411 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 412 413 /* Inbound 2GB range starting at 0 */ 414 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 415 416 /* This drives busses 0 to 0x3f */ 417 bus-range = <0x0 0x3f>; 418 419 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 420 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 421 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 422 }; 423 424 PCIE0: pciex@d00000000 { 425 device_type = "pci"; 426 #interrupt-cells = <1>; 427 #size-cells = <2>; 428 #address-cells = <3>; 429 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 430 primary; 431 port = <0x0>; /* port number */ 432 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 433 0x0000000c 0x08010000 0x00001000>; /* Registers */ 434 dcr-reg = <0x100 0x020>; 435 sdr-base = <0x300>; 436 437 /* Outbound ranges, one memory and one IO, 438 * later cannot be changed 439 */ 440 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 441 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 442 443 /* Inbound 2GB range starting at 0 */ 444 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 445 446 /* This drives busses 40 to 0x7f */ 447 bus-range = <0x40 0x7f>; 448 449 /* Legacy interrupts (note the weird polarity, the bridge seems 450 * to invert PCIe legacy interrupts). 451 * We are de-swizzling here because the numbers are actually for 452 * port of the root complex virtual P2P bridge. But I want 453 * to avoid putting a node for it in the tree, so the numbers 454 * below are basically de-swizzled numbers. 455 * The real slot is on idsel 0, so the swizzling is 1:1 456 */ 457 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 458 interrupt-map = < 459 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 460 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 461 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 462 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 463 }; 464 465 PCIE1: pciex@d20000000 { 466 device_type = "pci"; 467 #interrupt-cells = <1>; 468 #size-cells = <2>; 469 #address-cells = <3>; 470 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 471 primary; 472 port = <0x1>; /* port number */ 473 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 474 0x0000000c 0x08011000 0x00001000>; /* Registers */ 475 dcr-reg = <0x120 0x020>; 476 sdr-base = <0x340>; 477 478 /* Outbound ranges, one memory and one IO, 479 * later cannot be changed 480 */ 481 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 483 484 /* Inbound 2GB range starting at 0 */ 485 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 486 487 /* This drives busses 80 to 0xbf */ 488 bus-range = <0x80 0xbf>; 489 490 /* Legacy interrupts (note the weird polarity, the bridge seems 491 * to invert PCIe legacy interrupts). 492 * We are de-swizzling here because the numbers are actually for 493 * port of the root complex virtual P2P bridge. But I want 494 * to avoid putting a node for it in the tree, so the numbers 495 * below are basically de-swizzled numbers. 496 * The real slot is on idsel 0, so the swizzling is 1:1 497 */ 498 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 499 interrupt-map = < 500 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 501 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 502 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 503 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 504 }; 505 }; 506}; 507