19eec6cb1SIvan Mikhaylov/*
29eec6cb1SIvan Mikhaylov * Device Tree Source for FSP2
39eec6cb1SIvan Mikhaylov *
49eec6cb1SIvan Mikhaylov * Copyright 2010,2012 IBM Corp.
59eec6cb1SIvan Mikhaylov *
69eec6cb1SIvan Mikhaylov * This file is licensed under the terms of the GNU General Public
79eec6cb1SIvan Mikhaylov * License version 2.  This program is licensed "as is" without
89eec6cb1SIvan Mikhaylov * any warranty of any kind, whether express or implied.
99eec6cb1SIvan Mikhaylov */
109eec6cb1SIvan Mikhaylov
119eec6cb1SIvan Mikhaylov
129eec6cb1SIvan Mikhaylov/dts-v1/;
139eec6cb1SIvan Mikhaylov
149eec6cb1SIvan Mikhaylov/ {
159eec6cb1SIvan Mikhaylov	#address-cells = <2>;
169eec6cb1SIvan Mikhaylov	#size-cells = <1>;
179eec6cb1SIvan Mikhaylov	model = "ibm,fsp2";
189eec6cb1SIvan Mikhaylov	compatible = "ibm,fsp2";
199eec6cb1SIvan Mikhaylov	dcr-parent = <&{/cpus/cpu@0}>;
209eec6cb1SIvan Mikhaylov
219eec6cb1SIvan Mikhaylov	aliases {
229eec6cb1SIvan Mikhaylov		ethernet0 = &EMAC0;
239eec6cb1SIvan Mikhaylov		ethernet1 = &EMAC1;
249eec6cb1SIvan Mikhaylov		serial0 = &UART0;
259eec6cb1SIvan Mikhaylov	};
269eec6cb1SIvan Mikhaylov
279eec6cb1SIvan Mikhaylov	cpus {
289eec6cb1SIvan Mikhaylov		#address-cells = <1>;
299eec6cb1SIvan Mikhaylov		#size-cells = <0>;
309eec6cb1SIvan Mikhaylov
319eec6cb1SIvan Mikhaylov		cpu@0 {
329eec6cb1SIvan Mikhaylov			device_type = "cpu";
339eec6cb1SIvan Mikhaylov			model = "PowerPC, 476FSP2";
349eec6cb1SIvan Mikhaylov			reg = <0x0>;
359eec6cb1SIvan Mikhaylov			clock-frequency = <0>;    /* Filled in by cuboot */
369eec6cb1SIvan Mikhaylov			timebase-frequency = <0>; /* Filled in by cuboot */
379eec6cb1SIvan Mikhaylov			i-cache-line-size = <32>;
389eec6cb1SIvan Mikhaylov			d-cache-line-size = <32>;
399eec6cb1SIvan Mikhaylov			d-cache-size = <32768>;
409eec6cb1SIvan Mikhaylov			i-cache-size = <32768>;
419eec6cb1SIvan Mikhaylov			dcr-controller;
429eec6cb1SIvan Mikhaylov			dcr-access-method = "native";
439eec6cb1SIvan Mikhaylov		};
449eec6cb1SIvan Mikhaylov	};
459eec6cb1SIvan Mikhaylov
469eec6cb1SIvan Mikhaylov	memory {
479eec6cb1SIvan Mikhaylov		device_type = "memory";
489eec6cb1SIvan Mikhaylov		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by
499eec6cb1SIvan Mikhaylov							     cuboot */
509eec6cb1SIvan Mikhaylov	};
519eec6cb1SIvan Mikhaylov
529eec6cb1SIvan Mikhaylov	clocks {
539eec6cb1SIvan Mikhaylov		mmc_clk: mmc_clk {
549eec6cb1SIvan Mikhaylov			compatible = "fixed-clock";
559eec6cb1SIvan Mikhaylov			clock-frequency = <50000000>;
569eec6cb1SIvan Mikhaylov			clock-output-names = "mmc_clk";
579eec6cb1SIvan Mikhaylov		};
589eec6cb1SIvan Mikhaylov	};
599eec6cb1SIvan Mikhaylov
609eec6cb1SIvan Mikhaylov	UIC0: uic0 {
619eec6cb1SIvan Mikhaylov		#address-cells = <0>;
629eec6cb1SIvan Mikhaylov		#size-cells = <0>;
639eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
649eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
659eec6cb1SIvan Mikhaylov		interrupt-controller;
669eec6cb1SIvan Mikhaylov		cell-index = <0>;
679eec6cb1SIvan Mikhaylov		dcr-reg = <0x2c0 0x8>;
689eec6cb1SIvan Mikhaylov	};
699eec6cb1SIvan Mikhaylov
709eec6cb1SIvan Mikhaylov	/* "interrupts" field is <bit level bit level>
719eec6cb1SIvan Mikhaylov	   first pair is non-critical, second is critical */
729eec6cb1SIvan Mikhaylov	UIC1_0: uic1_0 {
739eec6cb1SIvan Mikhaylov		#address-cells = <0>;
749eec6cb1SIvan Mikhaylov		#size-cells = <0>;
759eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
769eec6cb1SIvan Mikhaylov
779eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
789eec6cb1SIvan Mikhaylov		interrupt-controller;
799eec6cb1SIvan Mikhaylov		cell-index = <1>;
809eec6cb1SIvan Mikhaylov		dcr-reg = <0x2c8 0x8>;
819eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
829eec6cb1SIvan Mikhaylov		interrupts = <21 0x4 4 0x84>;
839eec6cb1SIvan Mikhaylov	};
849eec6cb1SIvan Mikhaylov
859eec6cb1SIvan Mikhaylov	/* PSI and DMA */
869eec6cb1SIvan Mikhaylov	UIC1_1: uic1_1 {
879eec6cb1SIvan Mikhaylov		#address-cells = <0>;
889eec6cb1SIvan Mikhaylov		#size-cells = <0>;
899eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
909eec6cb1SIvan Mikhaylov
919eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
929eec6cb1SIvan Mikhaylov		interrupt-controller;
939eec6cb1SIvan Mikhaylov		cell-index = <2>;
949eec6cb1SIvan Mikhaylov		dcr-reg = <0x350 0x8>;
959eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
969eec6cb1SIvan Mikhaylov		interrupts = <22 0x4 5 0x84>;
979eec6cb1SIvan Mikhaylov	};
989eec6cb1SIvan Mikhaylov
999eec6cb1SIvan Mikhaylov	/* Ethernet and USB */
1009eec6cb1SIvan Mikhaylov	UIC1_2: uic1_2 {
1019eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1029eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1039eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1049eec6cb1SIvan Mikhaylov
1059eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1069eec6cb1SIvan Mikhaylov		interrupt-controller;
1079eec6cb1SIvan Mikhaylov		cell-index = <3>;
1089eec6cb1SIvan Mikhaylov		dcr-reg = <0x358 0x8>;
1099eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
1109eec6cb1SIvan Mikhaylov		interrupts = <23 0x4 6 0x84>;
1119eec6cb1SIvan Mikhaylov	};
1129eec6cb1SIvan Mikhaylov
1139eec6cb1SIvan Mikhaylov	/* PLB Errors */
1149eec6cb1SIvan Mikhaylov	UIC1_3: uic1_3 {
1159eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1169eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1179eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1189eec6cb1SIvan Mikhaylov
1199eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1209eec6cb1SIvan Mikhaylov		interrupt-controller;
1219eec6cb1SIvan Mikhaylov		cell-index = <4>;
1229eec6cb1SIvan Mikhaylov		dcr-reg = <0x360 0x8>;
1239eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
1249eec6cb1SIvan Mikhaylov		interrupts = <24 0x4 7 0x84>;
1259eec6cb1SIvan Mikhaylov	};
1269eec6cb1SIvan Mikhaylov
1279eec6cb1SIvan Mikhaylov	UIC1_4: uic1_4 {
1289eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1299eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1309eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1319eec6cb1SIvan Mikhaylov
1329eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1339eec6cb1SIvan Mikhaylov		interrupt-controller;
1349eec6cb1SIvan Mikhaylov		cell-index = <5>;
1359eec6cb1SIvan Mikhaylov		dcr-reg = <0x368 0x8>;
1369eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
1379eec6cb1SIvan Mikhaylov		interrupts = <25 0x4 8 0x84>;
1389eec6cb1SIvan Mikhaylov	};
1399eec6cb1SIvan Mikhaylov
1409eec6cb1SIvan Mikhaylov	UIC1_5: uic1_5 {
1419eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1429eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1439eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1449eec6cb1SIvan Mikhaylov
1459eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1469eec6cb1SIvan Mikhaylov		interrupt-controller;
1479eec6cb1SIvan Mikhaylov		cell-index = <6>;
1489eec6cb1SIvan Mikhaylov		dcr-reg = <0x370 0x8>;
1499eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC0>;
1509eec6cb1SIvan Mikhaylov		interrupts = <26 0x4 9 0x84>;
1519eec6cb1SIvan Mikhaylov	};
1529eec6cb1SIvan Mikhaylov
1539eec6cb1SIvan Mikhaylov	/* 2nd level UICs for FSI */
1549eec6cb1SIvan Mikhaylov	UIC2_0: uic2_0 {
1559eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1569eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1579eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1589eec6cb1SIvan Mikhaylov
1599eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1609eec6cb1SIvan Mikhaylov		interrupt-controller;
1619eec6cb1SIvan Mikhaylov		cell-index = <7>;
1629eec6cb1SIvan Mikhaylov		dcr-reg = <0x2d0 0x8>;
1639eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
1649eec6cb1SIvan Mikhaylov		interrupts = <16 0x4 0 0x84>;
1659eec6cb1SIvan Mikhaylov	};
1669eec6cb1SIvan Mikhaylov
1679eec6cb1SIvan Mikhaylov	UIC2_1: uic2_1 {
1689eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1699eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1709eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1719eec6cb1SIvan Mikhaylov
1729eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1739eec6cb1SIvan Mikhaylov		interrupt-controller;
1749eec6cb1SIvan Mikhaylov		cell-index = <8>;
1759eec6cb1SIvan Mikhaylov		dcr-reg = <0x2d8 0x8>;
1769eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
1779eec6cb1SIvan Mikhaylov		interrupts = <17 0x4 1 0x84>;
1789eec6cb1SIvan Mikhaylov	};
1799eec6cb1SIvan Mikhaylov
1809eec6cb1SIvan Mikhaylov	UIC2_2: uic2_2 {
1819eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1829eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1839eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1849eec6cb1SIvan Mikhaylov
1859eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1869eec6cb1SIvan Mikhaylov		interrupt-controller;
1879eec6cb1SIvan Mikhaylov		cell-index = <9>;
1889eec6cb1SIvan Mikhaylov		dcr-reg = <0x2e0 0x8>;
1899eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
1909eec6cb1SIvan Mikhaylov		interrupts = <18 0x4 2 0x84>;
1919eec6cb1SIvan Mikhaylov	};
1929eec6cb1SIvan Mikhaylov
1939eec6cb1SIvan Mikhaylov	UIC2_3: uic2_3 {
1949eec6cb1SIvan Mikhaylov		#address-cells = <0>;
1959eec6cb1SIvan Mikhaylov		#size-cells = <0>;
1969eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
1979eec6cb1SIvan Mikhaylov
1989eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
1999eec6cb1SIvan Mikhaylov		interrupt-controller;
2009eec6cb1SIvan Mikhaylov		cell-index = <10>;
2019eec6cb1SIvan Mikhaylov		dcr-reg = <0x2e8 0x8>;
2029eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2039eec6cb1SIvan Mikhaylov		interrupts = <19 0x4 3 0x84>;
2049eec6cb1SIvan Mikhaylov	};
2059eec6cb1SIvan Mikhaylov
2069eec6cb1SIvan Mikhaylov	UIC2_4: uic2_4 {
2079eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2089eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2099eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2109eec6cb1SIvan Mikhaylov
2119eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2129eec6cb1SIvan Mikhaylov		interrupt-controller;
2139eec6cb1SIvan Mikhaylov		cell-index = <11>;
2149eec6cb1SIvan Mikhaylov		dcr-reg = <0x2f0 0x8>;
2159eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2169eec6cb1SIvan Mikhaylov		interrupts = <20 0x4 4 0x84>;
2179eec6cb1SIvan Mikhaylov	};
2189eec6cb1SIvan Mikhaylov
2199eec6cb1SIvan Mikhaylov	UIC2_5: uic2_5 {
2209eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2219eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2229eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2239eec6cb1SIvan Mikhaylov
2249eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2259eec6cb1SIvan Mikhaylov		interrupt-controller;
2269eec6cb1SIvan Mikhaylov		cell-index = <12>;
2279eec6cb1SIvan Mikhaylov		dcr-reg = <0x2f8 0x8>;
2289eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2299eec6cb1SIvan Mikhaylov		interrupts = <21 0x4 5 0x84>;
2309eec6cb1SIvan Mikhaylov	};
2319eec6cb1SIvan Mikhaylov
2329eec6cb1SIvan Mikhaylov	UIC2_6: uic2_6 {
2339eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2349eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2359eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2369eec6cb1SIvan Mikhaylov
2379eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2389eec6cb1SIvan Mikhaylov		interrupt-controller;
2399eec6cb1SIvan Mikhaylov		cell-index = <13>;
2409eec6cb1SIvan Mikhaylov		dcr-reg = <0x300 0x8>;
2419eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2429eec6cb1SIvan Mikhaylov		interrupts = <22 0x4 6 0x84>;
2439eec6cb1SIvan Mikhaylov	};
2449eec6cb1SIvan Mikhaylov
2459eec6cb1SIvan Mikhaylov	UIC2_7: uic2_7 {
2469eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2479eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2489eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2499eec6cb1SIvan Mikhaylov
2509eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2519eec6cb1SIvan Mikhaylov		interrupt-controller;
2529eec6cb1SIvan Mikhaylov		cell-index = <14>;
2539eec6cb1SIvan Mikhaylov		dcr-reg = <0x308 0x8>;
2549eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2559eec6cb1SIvan Mikhaylov		interrupts = <23 0x4 7 0x84>;
2569eec6cb1SIvan Mikhaylov	};
2579eec6cb1SIvan Mikhaylov
2589eec6cb1SIvan Mikhaylov	UIC2_8: uic2_8 {
2599eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2609eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2619eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2629eec6cb1SIvan Mikhaylov
2639eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2649eec6cb1SIvan Mikhaylov		interrupt-controller;
2659eec6cb1SIvan Mikhaylov		cell-index = <15>;
2669eec6cb1SIvan Mikhaylov		dcr-reg = <0x310 0x8>;
2679eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2689eec6cb1SIvan Mikhaylov		interrupts = <24 0x4 8 0x84>;
2699eec6cb1SIvan Mikhaylov	};
2709eec6cb1SIvan Mikhaylov
2719eec6cb1SIvan Mikhaylov	UIC2_9: uic2_9 {
2729eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2739eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2749eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2759eec6cb1SIvan Mikhaylov
2769eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2779eec6cb1SIvan Mikhaylov		interrupt-controller;
2789eec6cb1SIvan Mikhaylov		cell-index = <16>;
2799eec6cb1SIvan Mikhaylov		dcr-reg = <0x318 0x8>;
2809eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2819eec6cb1SIvan Mikhaylov		interrupts = <25 0x4 9 0x84>;
2829eec6cb1SIvan Mikhaylov	};
2839eec6cb1SIvan Mikhaylov
2849eec6cb1SIvan Mikhaylov	UIC2_10: uic2_10 {
2859eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2869eec6cb1SIvan Mikhaylov		#size-cells = <0>;
2879eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
2889eec6cb1SIvan Mikhaylov
2899eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
2909eec6cb1SIvan Mikhaylov		interrupt-controller;
2919eec6cb1SIvan Mikhaylov		cell-index = <17>;
2929eec6cb1SIvan Mikhaylov		dcr-reg = <0x320 0x8>;
2939eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
2949eec6cb1SIvan Mikhaylov		interrupts = <26 0x4 10 0x84>;
2959eec6cb1SIvan Mikhaylov	};
2969eec6cb1SIvan Mikhaylov
2979eec6cb1SIvan Mikhaylov	UIC2_11: uic2_11 {
2989eec6cb1SIvan Mikhaylov		#address-cells = <0>;
2999eec6cb1SIvan Mikhaylov		#size-cells = <0>;
3009eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
3019eec6cb1SIvan Mikhaylov
3029eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
3039eec6cb1SIvan Mikhaylov		interrupt-controller;
3049eec6cb1SIvan Mikhaylov		cell-index = <18>;
3059eec6cb1SIvan Mikhaylov		dcr-reg = <0x328 0x8>;
3069eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
3079eec6cb1SIvan Mikhaylov		interrupts = <27 0x4 11 0x84>;
3089eec6cb1SIvan Mikhaylov	};
3099eec6cb1SIvan Mikhaylov
3109eec6cb1SIvan Mikhaylov	UIC2_12: uic2_12 {
3119eec6cb1SIvan Mikhaylov		#address-cells = <0>;
3129eec6cb1SIvan Mikhaylov		#size-cells = <0>;
3139eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
3149eec6cb1SIvan Mikhaylov
3159eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
3169eec6cb1SIvan Mikhaylov		interrupt-controller;
3179eec6cb1SIvan Mikhaylov		cell-index = <19>;
3189eec6cb1SIvan Mikhaylov		dcr-reg = <0x330 0x8>;
3199eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
3209eec6cb1SIvan Mikhaylov		interrupts = <28 0x4 12 0x84>;
3219eec6cb1SIvan Mikhaylov	};
3229eec6cb1SIvan Mikhaylov
3239eec6cb1SIvan Mikhaylov	UIC2_13: uic2_13 {
3249eec6cb1SIvan Mikhaylov		#address-cells = <0>;
3259eec6cb1SIvan Mikhaylov		#size-cells = <0>;
3269eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
3279eec6cb1SIvan Mikhaylov
3289eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
3299eec6cb1SIvan Mikhaylov		interrupt-controller;
3309eec6cb1SIvan Mikhaylov		cell-index = <20>;
3319eec6cb1SIvan Mikhaylov		dcr-reg = <0x338 0x8>;
3329eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
3339eec6cb1SIvan Mikhaylov		interrupts = <29 0x4 13 0x84>;
3349eec6cb1SIvan Mikhaylov	};
3359eec6cb1SIvan Mikhaylov
3369eec6cb1SIvan Mikhaylov	UIC2_14: uic2_14 {
3379eec6cb1SIvan Mikhaylov		#address-cells = <0>;
3389eec6cb1SIvan Mikhaylov		#size-cells = <0>;
3399eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
3409eec6cb1SIvan Mikhaylov
3419eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
3429eec6cb1SIvan Mikhaylov		interrupt-controller;
3439eec6cb1SIvan Mikhaylov		cell-index = <21>;
3449eec6cb1SIvan Mikhaylov		dcr-reg = <0x340 0x8>;
3459eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
3469eec6cb1SIvan Mikhaylov		interrupts = <30 0x4 14 0x84>;
3479eec6cb1SIvan Mikhaylov	};
3489eec6cb1SIvan Mikhaylov
3499eec6cb1SIvan Mikhaylov	UIC2_15: uic2_15 {
3509eec6cb1SIvan Mikhaylov		#address-cells = <0>;
3519eec6cb1SIvan Mikhaylov		#size-cells = <0>;
3529eec6cb1SIvan Mikhaylov		#interrupt-cells = <2>;
3539eec6cb1SIvan Mikhaylov
3549eec6cb1SIvan Mikhaylov		compatible = "ibm,uic";
3559eec6cb1SIvan Mikhaylov		interrupt-controller;
3569eec6cb1SIvan Mikhaylov		cell-index = <22>;
3579eec6cb1SIvan Mikhaylov		dcr-reg = <0x348 0x8>;
3589eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_0>;
3599eec6cb1SIvan Mikhaylov		interrupts = <31 0x4 15 0x84>;
3609eec6cb1SIvan Mikhaylov	};
3619eec6cb1SIvan Mikhaylov
3629eec6cb1SIvan Mikhaylov	mmc0: sdhci@020c0000 {
3639eec6cb1SIvan Mikhaylov		compatible	= "st,sdhci-stih407", "st,sdhci";
3649eec6cb1SIvan Mikhaylov		status		= "disabled";
3659eec6cb1SIvan Mikhaylov		reg		= <0x020c0000 0x20000>;
3669eec6cb1SIvan Mikhaylov		reg-names	= "mmc";
3679eec6cb1SIvan Mikhaylov		interrupt-parent = <&UIC1_3>;
3689eec6cb1SIvan Mikhaylov		interrupts	= <21 0x4 22 0x4>;
3699eec6cb1SIvan Mikhaylov		interrupt-names	= "mmcirq";
3709eec6cb1SIvan Mikhaylov		pinctrl-names	= "default";
3719eec6cb1SIvan Mikhaylov		pinctrl-0	= <>;
3729eec6cb1SIvan Mikhaylov		clock-names	= "mmc";
3739eec6cb1SIvan Mikhaylov		clocks		= <&mmc_clk>;
3749eec6cb1SIvan Mikhaylov	};
3759eec6cb1SIvan Mikhaylov
3769eec6cb1SIvan Mikhaylov	plb6 {
3779eec6cb1SIvan Mikhaylov		compatible = "ibm,plb6";
3789eec6cb1SIvan Mikhaylov		#address-cells = <2>;
3799eec6cb1SIvan Mikhaylov		#size-cells = <1>;
3809eec6cb1SIvan Mikhaylov		ranges;
3819eec6cb1SIvan Mikhaylov
3829eec6cb1SIvan Mikhaylov		MCW0: memory-controller-wrapper {
3839eec6cb1SIvan Mikhaylov			compatible = "ibm,cw-476fsp2";
3849eec6cb1SIvan Mikhaylov			dcr-reg = <0x11111800 0x40>;
3859eec6cb1SIvan Mikhaylov		};
3869eec6cb1SIvan Mikhaylov
3879eec6cb1SIvan Mikhaylov		MCIF0: memory-controller {
3889eec6cb1SIvan Mikhaylov			compatible = "ibm,sdram-476fsp2", "ibm,sdram-4xx-ddr3";
3899eec6cb1SIvan Mikhaylov			dcr-reg = <0x11120000 0x10000>;
3909eec6cb1SIvan Mikhaylov			mcer-device = <&MCW0>;
3919eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
3929eec6cb1SIvan Mikhaylov			interrupts = <10 0x84   /* ECC UE */
3939eec6cb1SIvan Mikhaylov				      11 0x84>; /* ECC CE */
3949eec6cb1SIvan Mikhaylov		};
3959eec6cb1SIvan Mikhaylov	};
3969eec6cb1SIvan Mikhaylov
3979eec6cb1SIvan Mikhaylov	plb4 {
3989eec6cb1SIvan Mikhaylov		compatible = "ibm,plb4";
3999eec6cb1SIvan Mikhaylov		#address-cells = <1>;
4009eec6cb1SIvan Mikhaylov		#size-cells = <1>;
4019eec6cb1SIvan Mikhaylov		ranges = <0x00000000 0x00000010 0x00000000 0x80000000
4029eec6cb1SIvan Mikhaylov			  0x80000000 0x00000010 0x80000000 0x80000000>;
4039eec6cb1SIvan Mikhaylov		clock-frequency = <333333334>;
4049eec6cb1SIvan Mikhaylov
4059eec6cb1SIvan Mikhaylov		plb6-system-hung-irq {
4069eec6cb1SIvan Mikhaylov			compatible = "ibm,bus-error-irq";
4079eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4089eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4099eec6cb1SIvan Mikhaylov			interrupts = <0 0x84>;
4109eec6cb1SIvan Mikhaylov		};
4119eec6cb1SIvan Mikhaylov
4129eec6cb1SIvan Mikhaylov		l2-error-irq {
4139eec6cb1SIvan Mikhaylov			compatible = "ibm,bus-error-irq";
4149eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4159eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4169eec6cb1SIvan Mikhaylov			interrupts = <20 0x84>;
4179eec6cb1SIvan Mikhaylov		};
4189eec6cb1SIvan Mikhaylov
4199eec6cb1SIvan Mikhaylov		plb6-plb4-irq {
4209eec6cb1SIvan Mikhaylov			compatible = "ibm,bus-error-irq";
4219eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4229eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4239eec6cb1SIvan Mikhaylov			interrupts = <1 0x84>;
4249eec6cb1SIvan Mikhaylov		};
4259eec6cb1SIvan Mikhaylov
4269eec6cb1SIvan Mikhaylov		plb4-ahb-irq {
4279eec6cb1SIvan Mikhaylov			compatible = "ibm,bus-error-irq";
4289eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4299eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_3>;
4309eec6cb1SIvan Mikhaylov			interrupts = <20 0x84>;
4319eec6cb1SIvan Mikhaylov		};
4329eec6cb1SIvan Mikhaylov
4339eec6cb1SIvan Mikhaylov		opbd-error-irq {
4349eec6cb1SIvan Mikhaylov			compatible = "ibm,opbd-error-irq";
4359eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4369eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_4>;
4379eec6cb1SIvan Mikhaylov			interrupts = <5 0x84>;
4389eec6cb1SIvan Mikhaylov		};
4399eec6cb1SIvan Mikhaylov
4409eec6cb1SIvan Mikhaylov		cmu-error-irq {
4419eec6cb1SIvan Mikhaylov			compatible = "ibm,cmu-error-irq";
4429eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4439eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4449eec6cb1SIvan Mikhaylov			interrupts = <28 0x84>;
4459eec6cb1SIvan Mikhaylov		};
4469eec6cb1SIvan Mikhaylov
4479eec6cb1SIvan Mikhaylov		conf-error-irq {
4489eec6cb1SIvan Mikhaylov			compatible = "ibm,conf-error-irq";
4499eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4509eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_4>;
4519eec6cb1SIvan Mikhaylov			interrupts = <11 0x84>;
4529eec6cb1SIvan Mikhaylov		};
4539eec6cb1SIvan Mikhaylov
4549eec6cb1SIvan Mikhaylov		mc-ue-irq {
4559eec6cb1SIvan Mikhaylov			compatible = "ibm,mc-ue-irq";
4569eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4579eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4589eec6cb1SIvan Mikhaylov			interrupts = <10 0x84>;
4599eec6cb1SIvan Mikhaylov		};
4609eec6cb1SIvan Mikhaylov
4619eec6cb1SIvan Mikhaylov		reset-warning-irq {
4629eec6cb1SIvan Mikhaylov			compatible = "ibm,reset-warning-irq";
4639eec6cb1SIvan Mikhaylov			#interrupt-cells = <2>;
4649eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC0>;
4659eec6cb1SIvan Mikhaylov			interrupts = <17 0x84>;
4669eec6cb1SIvan Mikhaylov		};
4679eec6cb1SIvan Mikhaylov
4689eec6cb1SIvan Mikhaylov		MAL0: mcmal0 {
4699eec6cb1SIvan Mikhaylov			#interrupt-cells = <1>;
4709eec6cb1SIvan Mikhaylov			#address-cells = <0>;
4719eec6cb1SIvan Mikhaylov			#size-cells = <0>;
4729eec6cb1SIvan Mikhaylov			compatible = "ibm,mcmal";
4739eec6cb1SIvan Mikhaylov			dcr-reg = <0x80 0x80>;
4749eec6cb1SIvan Mikhaylov			num-tx-chans = <1>;
4759eec6cb1SIvan Mikhaylov			num-rx-chans = <1>;
4769eec6cb1SIvan Mikhaylov			interrupt-parent = <&MAL0>;
4779eec6cb1SIvan Mikhaylov			interrupts = <0 1 2 3 4>;
4789eec6cb1SIvan Mikhaylov			/* index interrupt-parent interrupt# type */
4799eec6cb1SIvan Mikhaylov			interrupt-map = </*TXEOB*/ 0 &UIC1_2 4 0x4
4809eec6cb1SIvan Mikhaylov					 /*RXEOB*/ 1 &UIC1_2 3 0x4
4819eec6cb1SIvan Mikhaylov					 /*SERR*/  2 &UIC1_2 7 0x4
4829eec6cb1SIvan Mikhaylov					 /*TXDE*/  3 &UIC1_2 6 0x4
4839eec6cb1SIvan Mikhaylov					 /*RXDE*/  4 &UIC1_2 5 0x4>;
4849eec6cb1SIvan Mikhaylov		};
4859eec6cb1SIvan Mikhaylov
4869eec6cb1SIvan Mikhaylov		MAL1: mcmal1 {
4879eec6cb1SIvan Mikhaylov			#interrupt-cells = <1>;
4889eec6cb1SIvan Mikhaylov			#address-cells = <0>;
4899eec6cb1SIvan Mikhaylov			#size-cells = <0>;
4909eec6cb1SIvan Mikhaylov			compatible = "ibm,mcmal";
4919eec6cb1SIvan Mikhaylov			dcr-reg = <0x100 0x80>;
4929eec6cb1SIvan Mikhaylov			num-tx-chans = <1>;
4939eec6cb1SIvan Mikhaylov			num-rx-chans = <1>;
4949eec6cb1SIvan Mikhaylov			interrupt-parent = <&MAL1>;
4959eec6cb1SIvan Mikhaylov			interrupts = <0 1 2 3 4>;
4969eec6cb1SIvan Mikhaylov			/* index interrupt-parent interrupt# type */
4979eec6cb1SIvan Mikhaylov			interrupt-map = </*TXEOB*/ 0 &UIC1_2 12 0x4
4989eec6cb1SIvan Mikhaylov					 /*RXEOB*/ 1 &UIC1_2 11 0x4
4999eec6cb1SIvan Mikhaylov					 /*SERR*/  2 &UIC1_2 15 0x4
5009eec6cb1SIvan Mikhaylov					 /*TXDE*/  3 &UIC1_2 14 0x4
5019eec6cb1SIvan Mikhaylov					 /*RXDE*/  4 &UIC1_2 13 0x4>;
5029eec6cb1SIvan Mikhaylov		};
5039eec6cb1SIvan Mikhaylov
5049eec6cb1SIvan Mikhaylov		opb {
5059eec6cb1SIvan Mikhaylov			compatible = "ibm,opb";
5069eec6cb1SIvan Mikhaylov			#address-cells = <1>;
5079eec6cb1SIvan Mikhaylov			#size-cells = <1>;
5089eec6cb1SIvan Mikhaylov			ranges; // pass-thru to parent bus
5099eec6cb1SIvan Mikhaylov			clock-frequency = <83333334>;
5109eec6cb1SIvan Mikhaylov
5119eec6cb1SIvan Mikhaylov			EMAC0: ethernet@b0000000 {
5129eec6cb1SIvan Mikhaylov				linux,network-index = <0>;
5139eec6cb1SIvan Mikhaylov				device_type = "network";
5149eec6cb1SIvan Mikhaylov				compatible = "ibm,emac4sync";
5159eec6cb1SIvan Mikhaylov				has-inverted-stacr-oc;
5169eec6cb1SIvan Mikhaylov				interrupt-parent = <&UIC1_2>;
5179eec6cb1SIvan Mikhaylov				interrupts = <1 0x4 0 0x4>;
5189eec6cb1SIvan Mikhaylov				reg = <0xb0000000 0x100>;
5199eec6cb1SIvan Mikhaylov				local-mac-address = [000000000000]; /* Filled in by
5209eec6cb1SIvan Mikhaylov							       cuboot */
5219eec6cb1SIvan Mikhaylov				mal-device = <&MAL0>;
5229eec6cb1SIvan Mikhaylov				mal-tx-channel = <0>;
5239eec6cb1SIvan Mikhaylov				mal-rx-channel = <0>;
5249eec6cb1SIvan Mikhaylov				cell-index = <0>;
5259eec6cb1SIvan Mikhaylov				max-frame-size = <1500>;
5269eec6cb1SIvan Mikhaylov				rx-fifo-size = <4096>;
5279eec6cb1SIvan Mikhaylov				tx-fifo-size = <4096>;
5289eec6cb1SIvan Mikhaylov				rx-fifo-size-gige = <16384>;
5299eec6cb1SIvan Mikhaylov				tx-fifo-size-gige = <8192>;
5309eec6cb1SIvan Mikhaylov				phy-address = <1>;
5319eec6cb1SIvan Mikhaylov				phy-mode = "rgmii";
5329eec6cb1SIvan Mikhaylov				phy-map = <00000003>;
5339eec6cb1SIvan Mikhaylov				rgmii-device = <&RGMII>;
5349eec6cb1SIvan Mikhaylov				rgmii-channel = <0>;
5359eec6cb1SIvan Mikhaylov			};
5369eec6cb1SIvan Mikhaylov
5379eec6cb1SIvan Mikhaylov			EMAC1: ethernet@b0000100 {
5389eec6cb1SIvan Mikhaylov				linux,network-index = <1>;
5399eec6cb1SIvan Mikhaylov				device_type = "network";
5409eec6cb1SIvan Mikhaylov				compatible = "ibm,emac4sync";
5419eec6cb1SIvan Mikhaylov				has-inverted-stacr-oc;
5429eec6cb1SIvan Mikhaylov				interrupt-parent = <&UIC1_2>;
5439eec6cb1SIvan Mikhaylov				interrupts = <9 0x4 8 0x4>;
5449eec6cb1SIvan Mikhaylov				reg = <0xb0000100 0x100>;
5459eec6cb1SIvan Mikhaylov				local-mac-address = [000000000000]; /* Filled in by
5469eec6cb1SIvan Mikhaylov							       cuboot */
5479eec6cb1SIvan Mikhaylov				mal-device = <&MAL1>;
5489eec6cb1SIvan Mikhaylov				mal-tx-channel = <0>;
5499eec6cb1SIvan Mikhaylov				mal-rx-channel = <0>;
5509eec6cb1SIvan Mikhaylov				cell-index = <1>;
5519eec6cb1SIvan Mikhaylov				max-frame-size = <1500>;
5529eec6cb1SIvan Mikhaylov				rx-fifo-size = <4096>;
5539eec6cb1SIvan Mikhaylov				tx-fifo-size = <4096>;
5549eec6cb1SIvan Mikhaylov				rx-fifo-size-gige = <16384>;
5559eec6cb1SIvan Mikhaylov				tx-fifo-size-gige = <8192>;
5569eec6cb1SIvan Mikhaylov				phy-address = <2>;
5579eec6cb1SIvan Mikhaylov				phy-mode = "rgmii";
5589eec6cb1SIvan Mikhaylov				phy-map = <00000003>;
5599eec6cb1SIvan Mikhaylov				rgmii-device = <&RGMII>;
5609eec6cb1SIvan Mikhaylov				rgmii-channel = <1>;
5619eec6cb1SIvan Mikhaylov			};
5629eec6cb1SIvan Mikhaylov
5639eec6cb1SIvan Mikhaylov			RGMII: rgmii@b0000600 {
5649eec6cb1SIvan Mikhaylov				compatible = "ibm,rgmii";
5659eec6cb1SIvan Mikhaylov				has-mdio;
5669eec6cb1SIvan Mikhaylov				reg = <0xb0000600 0x8>;
5679eec6cb1SIvan Mikhaylov			};
5689eec6cb1SIvan Mikhaylov
5699eec6cb1SIvan Mikhaylov			UART0: serial@b0020000 {
5709eec6cb1SIvan Mikhaylov				device_type = "serial";
5719eec6cb1SIvan Mikhaylov				compatible = "ns16550";
5729eec6cb1SIvan Mikhaylov				reg = <0xb0020000 0x8>;
5739eec6cb1SIvan Mikhaylov				virtual-reg = <0xb0020000>;
5749eec6cb1SIvan Mikhaylov				clock-frequency = <20833333>;
5759eec6cb1SIvan Mikhaylov				current-speed = <115200>;
5769eec6cb1SIvan Mikhaylov				interrupt-parent = <&UIC0>;
5779eec6cb1SIvan Mikhaylov				interrupts = <31 0x4>;
5789eec6cb1SIvan Mikhaylov			};
5799eec6cb1SIvan Mikhaylov		};
5809eec6cb1SIvan Mikhaylov
5819eec6cb1SIvan Mikhaylov		OHCI1: ohci@02040000 {
5829eec6cb1SIvan Mikhaylov			compatible = "ohci-le";
5839eec6cb1SIvan Mikhaylov			reg = <0x02040000 0xa0>;
5849eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_3>;
5859eec6cb1SIvan Mikhaylov			interrupts = <28 0x8 29 0x8>;
5869eec6cb1SIvan Mikhaylov		};
5879eec6cb1SIvan Mikhaylov
5889eec6cb1SIvan Mikhaylov		OHCI2: ohci@02080000 {
5899eec6cb1SIvan Mikhaylov			compatible = "ohci-le";
5909eec6cb1SIvan Mikhaylov			reg = <0x02080000 0xa0>;
5919eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_3>;
5929eec6cb1SIvan Mikhaylov			interrupts = <30 0x8 31 0x8>;
5939eec6cb1SIvan Mikhaylov		};
5949eec6cb1SIvan Mikhaylov
5959eec6cb1SIvan Mikhaylov		EHCI: ehci@02000000 {
5969eec6cb1SIvan Mikhaylov			compatible = "usb-ehci";
5979eec6cb1SIvan Mikhaylov			reg = <0x02000000 0xa4>;
5989eec6cb1SIvan Mikhaylov			interrupt-parent = <&UIC1_3>;
5999eec6cb1SIvan Mikhaylov			interrupts = <23 0x4>;
6009eec6cb1SIvan Mikhaylov		};
6019eec6cb1SIvan Mikhaylov
6029eec6cb1SIvan Mikhaylov	};
6039eec6cb1SIvan Mikhaylov
6049eec6cb1SIvan Mikhaylov	chosen {
6059eec6cb1SIvan Mikhaylov		linux,stdout-path = "/plb/opb/serial@b0020000";
6069eec6cb1SIvan Mikhaylov		bootargs = "console=ttyS0,115200 rw log_buf_len=32768 debug";
6079eec6cb1SIvan Mikhaylov	};
6089eec6cb1SIvan Mikhaylov};
609