1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40	compatible = "fsl,T4240";
41	#address-cells = <2>;
42	#size-cells = <2>;
43	interrupt-parent = <&mpic>;
44
45	aliases {
46		ccsr = &soc;
47
48		serial0 = &serial0;
49		serial1 = &serial1;
50		serial2 = &serial2;
51		serial3 = &serial3;
52		crypto = &crypto;
53		pci0 = &pci0;
54		pci1 = &pci1;
55		pci2 = &pci2;
56		pci3 = &pci3;
57		dma0 = &dma0;
58		dma1 = &dma1;
59		sdhc = &sdhc;
60	};
61
62	cpus {
63		#address-cells = <1>;
64		#size-cells = <0>;
65
66		PowerPC,e6500@0 {
67			device_type = "cpu";
68			reg = <0 1>;
69			next-level-cache = <&L2_1>;
70		};
71		PowerPC,e6500@1 {
72			device_type = "cpu";
73			reg = <2 3>;
74			next-level-cache = <&L2_1>;
75		};
76		PowerPC,e6500@2 {
77			device_type = "cpu";
78			reg = <4 5>;
79			next-level-cache = <&L2_1>;
80		};
81		PowerPC,e6500@3 {
82			device_type = "cpu";
83			reg = <6 7>;
84			next-level-cache = <&L2_1>;
85		};
86		PowerPC,e6500@4 {
87			device_type = "cpu";
88			reg = <8 9>;
89			next-level-cache = <&L2_2>;
90		};
91		PowerPC,e6500@5 {
92			device_type = "cpu";
93			reg = <10 11>;
94			next-level-cache = <&L2_2>;
95		};
96		PowerPC,e6500@6 {
97			device_type = "cpu";
98			reg = <12 13>;
99			next-level-cache = <&L2_2>;
100		};
101		PowerPC,e6500@7 {
102			device_type = "cpu";
103			reg = <14 15>;
104			next-level-cache = <&L2_2>;
105		};
106		PowerPC,e6500@8 {
107			device_type = "cpu";
108			reg = <16 17>;
109			next-level-cache = <&L2_3>;
110		};
111		PowerPC,e6500@9 {
112			device_type = "cpu";
113			reg = <18 19>;
114			next-level-cache = <&L2_3>;
115		};
116		PowerPC,e6500@10 {
117			device_type = "cpu";
118			reg = <20 21>;
119			next-level-cache = <&L2_3>;
120		};
121		PowerPC,e6500@11 {
122			device_type = "cpu";
123			reg = <22 23>;
124			next-level-cache = <&L2_3>;
125		};
126	};
127};
128