1/* 2 * T4240 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2012 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&ifc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,ifc", "simple-bus"; 39 interrupts = <25 2 0 0>; 40}; 41 42/* controller at 0x240000 */ 43&pci0 { 44 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 interrupts = <20 2 0 0>; 50 pcie@0 { 51 #interrupt-cells = <1>; 52 #size-cells = <2>; 53 #address-cells = <3>; 54 device_type = "pci"; 55 interrupts = <20 2 0 0>; 56 interrupt-map-mask = <0xf800 0 0 7>; 57 interrupt-map = < 58 /* IDSEL 0x0 */ 59 0000 0 0 1 &mpic 40 1 0 0 60 0000 0 0 2 &mpic 1 1 0 0 61 0000 0 0 3 &mpic 2 1 0 0 62 0000 0 0 4 &mpic 3 1 0 0 63 >; 64 }; 65}; 66 67/* controller at 0x250000 */ 68&pci1 { 69 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 70 device_type = "pci"; 71 #size-cells = <2>; 72 #address-cells = <3>; 73 bus-range = <0 0xff>; 74 interrupts = <21 2 0 0>; 75 pcie@0 { 76 #interrupt-cells = <1>; 77 #size-cells = <2>; 78 #address-cells = <3>; 79 device_type = "pci"; 80 interrupts = <21 2 0 0>; 81 interrupt-map-mask = <0xf800 0 0 7>; 82 interrupt-map = < 83 /* IDSEL 0x0 */ 84 0000 0 0 1 &mpic 41 1 0 0 85 0000 0 0 2 &mpic 5 1 0 0 86 0000 0 0 3 &mpic 6 1 0 0 87 0000 0 0 4 &mpic 7 1 0 0 88 >; 89 }; 90}; 91 92/* controller at 0x260000 */ 93&pci2 { 94 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 95 device_type = "pci"; 96 #size-cells = <2>; 97 #address-cells = <3>; 98 bus-range = <0x0 0xff>; 99 interrupts = <22 2 0 0>; 100 pcie@0 { 101 #interrupt-cells = <1>; 102 #size-cells = <2>; 103 #address-cells = <3>; 104 device_type = "pci"; 105 interrupts = <22 2 0 0>; 106 interrupt-map-mask = <0xf800 0 0 7>; 107 interrupt-map = < 108 /* IDSEL 0x0 */ 109 0000 0 0 1 &mpic 42 1 0 0 110 0000 0 0 2 &mpic 9 1 0 0 111 0000 0 0 3 &mpic 10 1 0 0 112 0000 0 0 4 &mpic 11 1 0 0 113 >; 114 }; 115}; 116 117/* controller at 0x270000 */ 118&pci3 { 119 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 120 device_type = "pci"; 121 #size-cells = <2>; 122 #address-cells = <3>; 123 bus-range = <0x0 0xff>; 124 interrupts = <23 2 0 0>; 125 pcie@0 { 126 #interrupt-cells = <1>; 127 #size-cells = <2>; 128 #address-cells = <3>; 129 device_type = "pci"; 130 interrupts = <23 2 0 0>; 131 interrupt-map-mask = <0xf800 0 0 7>; 132 interrupt-map = < 133 /* IDSEL 0x0 */ 134 0000 0 0 1 &mpic 43 1 0 0 135 0000 0 0 2 &mpic 0 1 0 0 136 0000 0 0 3 &mpic 4 1 0 0 137 0000 0 0 4 &mpic 8 1 0 0 138 >; 139 }; 140}; 141 142&rio { 143 compatible = "fsl,srio"; 144 interrupts = <16 2 1 11>; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 port1 { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 cell-index = <1>; 153 }; 154 155 port2 { 156 #address-cells = <2>; 157 #size-cells = <2>; 158 cell-index = <2>; 159 }; 160}; 161 162&soc { 163 #address-cells = <1>; 164 #size-cells = <1>; 165 device_type = "soc"; 166 compatible = "simple-bus"; 167 168 soc-sram-error { 169 compatible = "fsl,soc-sram-error"; 170 interrupts = <16 2 1 29>; 171 }; 172 173 corenet-law@0 { 174 compatible = "fsl,corenet-law"; 175 reg = <0x0 0x1000>; 176 fsl,num-laws = <32>; 177 }; 178 179 ddr1: memory-controller@8000 { 180 compatible = "fsl,qoriq-memory-controller-v4.7", 181 "fsl,qoriq-memory-controller"; 182 reg = <0x8000 0x1000>; 183 interrupts = <16 2 1 23>; 184 }; 185 186 ddr2: memory-controller@9000 { 187 compatible = "fsl,qoriq-memory-controller-v4.7", 188 "fsl,qoriq-memory-controller"; 189 reg = <0x9000 0x1000>; 190 interrupts = <16 2 1 22>; 191 }; 192 193 ddr3: memory-controller@a000 { 194 compatible = "fsl,qoriq-memory-controller-v4.7", 195 "fsl,qoriq-memory-controller"; 196 reg = <0xa000 0x1000>; 197 interrupts = <16 2 1 21>; 198 }; 199 200 cpc: l3-cache-controller@10000 { 201 compatible = "fsl,t4240-l3-cache-controller", "cache"; 202 reg = <0x10000 0x1000 203 0x11000 0x1000 204 0x12000 0x1000>; 205 interrupts = <16 2 1 27 206 16 2 1 26 207 16 2 1 25>; 208 }; 209 210 corenet-cf@18000 { 211 compatible = "fsl,corenet-cf"; 212 reg = <0x18000 0x1000>; 213 interrupts = <16 2 1 31>; 214 fsl,ccf-num-csdids = <32>; 215 fsl,ccf-num-snoopids = <32>; 216 }; 217 218 iommu@20000 { 219 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 220 reg = <0x20000 0x6000>; 221 interrupts = < 222 24 2 0 0 223 16 2 1 30>; 224 }; 225 226/include/ "qoriq-mpic.dtsi" 227 228 guts: global-utilities@e0000 { 229 compatible = "fsl,t4240-device-config"; 230 reg = <0xe0000 0xe00>; 231 fsl,has-rstcr; 232 fsl,liodn-bits = <12>; 233 }; 234 235 clockgen: global-utilities@e1000 { 236 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2"; 237 reg = <0xe1000 0x1000>; 238 }; 239 240 rcpm: global-utilities@e2000 { 241 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2"; 242 reg = <0xe2000 0x1000>; 243 }; 244 245 sfp: sfp@e8000 { 246 compatible = "fsl,t4240-sfp"; 247 reg = <0xe8000 0x1000>; 248 }; 249 250 serdes: serdes@ea000 { 251 compatible = "fsl,t4240-serdes"; 252 reg = <0xea000 0x4000>; 253 }; 254 255/include/ "qoriq-dma-0.dtsi" 256/include/ "qoriq-dma-1.dtsi" 257 258/include/ "qoriq-espi-0.dtsi" 259 spi@110000 { 260 fsl,espi-num-chipselects = <4>; 261 }; 262 263/include/ "qoriq-esdhc-0.dtsi" 264 sdhc@114000 { 265 compatible = "fsl,t4240-esdhc", "fsl,esdhc"; 266 sdhci,auto-cmd12; 267 }; 268/include/ "qoriq-i2c-0.dtsi" 269/include/ "qoriq-i2c-1.dtsi" 270/include/ "qoriq-duart-0.dtsi" 271/include/ "qoriq-duart-1.dtsi" 272/include/ "qoriq-gpio-0.dtsi" 273/include/ "qoriq-gpio-1.dtsi" 274/include/ "qoriq-gpio-2.dtsi" 275/include/ "qoriq-gpio-3.dtsi" 276/include/ "qoriq-usb2-mph-0.dtsi" 277 usb0: usb@210000 { 278 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; 279 phy_type = "utmi"; 280 port0; 281 }; 282/include/ "qoriq-usb2-dr-0.dtsi" 283 usb1: usb@211000 { 284 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 285 dr_mode = "host"; 286 phy_type = "utmi"; 287 }; 288/include/ "qoriq-sata2-0.dtsi" 289/include/ "qoriq-sata2-1.dtsi" 290/include/ "qoriq-sec5.0-0.dtsi" 291 292 L2_1: l2-cache-controller@c20000 { 293 compatible = "fsl,t4240-l2-cache-controller"; 294 reg = <0xc20000 0x40000>; 295 next-level-cache = <&cpc>; 296 }; 297 L2_2: l2-cache-controller@c60000 { 298 compatible = "fsl,t4240-l2-cache-controller"; 299 reg = <0xc60000 0x40000>; 300 next-level-cache = <&cpc>; 301 }; 302 L2_3: l2-cache-controller@ca0000 { 303 compatible = "fsl,t4240-l2-cache-controller"; 304 reg = <0xca0000 0x40000>; 305 next-level-cache = <&cpc>; 306 }; 307}; 308