1/* 2 * T4240 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2012 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&ifc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,ifc", "simple-bus"; 39 interrupts = <25 2 0 0>; 40}; 41 42/* controller at 0x240000 */ 43&pci0 { 44 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 interrupts = <20 2 0 0>; 50 pcie@0 { 51 #interrupt-cells = <1>; 52 #size-cells = <2>; 53 #address-cells = <3>; 54 device_type = "pci"; 55 reg = <0 0 0 0 0>; 56 interrupts = <20 2 0 0>; 57 interrupt-map-mask = <0xf800 0 0 7>; 58 interrupt-map = < 59 /* IDSEL 0x0 */ 60 0000 0 0 1 &mpic 40 1 0 0 61 0000 0 0 2 &mpic 1 1 0 0 62 0000 0 0 3 &mpic 2 1 0 0 63 0000 0 0 4 &mpic 3 1 0 0 64 >; 65 }; 66}; 67 68/* controller at 0x250000 */ 69&pci1 { 70 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 71 device_type = "pci"; 72 #size-cells = <2>; 73 #address-cells = <3>; 74 bus-range = <0 0xff>; 75 interrupts = <21 2 0 0>; 76 pcie@0 { 77 #interrupt-cells = <1>; 78 #size-cells = <2>; 79 #address-cells = <3>; 80 device_type = "pci"; 81 reg = <0 0 0 0 0>; 82 interrupts = <21 2 0 0>; 83 interrupt-map-mask = <0xf800 0 0 7>; 84 interrupt-map = < 85 /* IDSEL 0x0 */ 86 0000 0 0 1 &mpic 41 1 0 0 87 0000 0 0 2 &mpic 5 1 0 0 88 0000 0 0 3 &mpic 6 1 0 0 89 0000 0 0 4 &mpic 7 1 0 0 90 >; 91 }; 92}; 93 94/* controller at 0x260000 */ 95&pci2 { 96 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 97 device_type = "pci"; 98 #size-cells = <2>; 99 #address-cells = <3>; 100 bus-range = <0x0 0xff>; 101 interrupts = <22 2 0 0>; 102 pcie@0 { 103 #interrupt-cells = <1>; 104 #size-cells = <2>; 105 #address-cells = <3>; 106 device_type = "pci"; 107 reg = <0 0 0 0 0>; 108 interrupts = <22 2 0 0>; 109 interrupt-map-mask = <0xf800 0 0 7>; 110 interrupt-map = < 111 /* IDSEL 0x0 */ 112 0000 0 0 1 &mpic 42 1 0 0 113 0000 0 0 2 &mpic 9 1 0 0 114 0000 0 0 3 &mpic 10 1 0 0 115 0000 0 0 4 &mpic 11 1 0 0 116 >; 117 }; 118}; 119 120/* controller at 0x270000 */ 121&pci3 { 122 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 123 device_type = "pci"; 124 #size-cells = <2>; 125 #address-cells = <3>; 126 bus-range = <0x0 0xff>; 127 interrupts = <23 2 0 0>; 128 pcie@0 { 129 #interrupt-cells = <1>; 130 #size-cells = <2>; 131 #address-cells = <3>; 132 device_type = "pci"; 133 reg = <0 0 0 0 0>; 134 interrupts = <23 2 0 0>; 135 interrupt-map-mask = <0xf800 0 0 7>; 136 interrupt-map = < 137 /* IDSEL 0x0 */ 138 0000 0 0 1 &mpic 43 1 0 0 139 0000 0 0 2 &mpic 0 1 0 0 140 0000 0 0 3 &mpic 4 1 0 0 141 0000 0 0 4 &mpic 8 1 0 0 142 >; 143 }; 144}; 145 146&rio { 147 compatible = "fsl,srio"; 148 interrupts = <16 2 1 11>; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 port1 { 154 #address-cells = <2>; 155 #size-cells = <2>; 156 cell-index = <1>; 157 }; 158 159 port2 { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 cell-index = <2>; 163 }; 164}; 165 166&dcsr { 167 #address-cells = <1>; 168 #size-cells = <1>; 169 compatible = "fsl,dcsr", "simple-bus"; 170 171 dcsr-epu@0 { 172 compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu"; 173 interrupts = <52 2 0 0 174 84 2 0 0 175 85 2 0 0 176 94 2 0 0 177 95 2 0 0>; 178 reg = <0x0 0x1000>; 179 }; 180 dcsr-npc { 181 compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc"; 182 reg = <0x1000 0x1000 0x1002000 0x10000>; 183 }; 184 dcsr-nxc@2000 { 185 compatible = "fsl,dcsr-nxc"; 186 reg = <0x2000 0x1000>; 187 }; 188 dcsr-corenet { 189 compatible = "fsl,dcsr-corenet"; 190 reg = <0x8000 0x1000 0x1A000 0x1000>; 191 }; 192 dcsr-dpaa@9000 { 193 compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa"; 194 reg = <0x9000 0x1000>; 195 }; 196 dcsr-ocn@11000 { 197 compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn"; 198 reg = <0x11000 0x1000>; 199 }; 200 dcsr-ddr@12000 { 201 compatible = "fsl,dcsr-ddr"; 202 dev-handle = <&ddr1>; 203 reg = <0x12000 0x1000>; 204 }; 205 dcsr-ddr@13000 { 206 compatible = "fsl,dcsr-ddr"; 207 dev-handle = <&ddr2>; 208 reg = <0x13000 0x1000>; 209 }; 210 dcsr-ddr@14000 { 211 compatible = "fsl,dcsr-ddr"; 212 dev-handle = <&ddr3>; 213 reg = <0x14000 0x1000>; 214 }; 215 dcsr-nal@18000 { 216 compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal"; 217 reg = <0x18000 0x1000>; 218 }; 219 dcsr-rcpm@22000 { 220 compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm"; 221 reg = <0x22000 0x1000>; 222 }; 223 dcsr-snpc@30000 { 224 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; 225 reg = <0x30000 0x1000 0x1022000 0x10000>; 226 }; 227 dcsr-snpc@31000 { 228 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; 229 reg = <0x31000 0x1000 0x1042000 0x10000>; 230 }; 231 dcsr-snpc@32000 { 232 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; 233 reg = <0x32000 0x1000 0x1062000 0x10000>; 234 }; 235 dcsr-cpu-sb-proxy@100000 { 236 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 237 cpu-handle = <&cpu0>; 238 reg = <0x100000 0x1000 0x101000 0x1000>; 239 }; 240 dcsr-cpu-sb-proxy@108000 { 241 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 242 cpu-handle = <&cpu1>; 243 reg = <0x108000 0x1000 0x109000 0x1000>; 244 }; 245 dcsr-cpu-sb-proxy@110000 { 246 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 247 cpu-handle = <&cpu2>; 248 reg = <0x110000 0x1000 0x111000 0x1000>; 249 }; 250 dcsr-cpu-sb-proxy@118000 { 251 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 252 cpu-handle = <&cpu3>; 253 reg = <0x118000 0x1000 0x119000 0x1000>; 254 }; 255 dcsr-cpu-sb-proxy@120000 { 256 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 257 cpu-handle = <&cpu4>; 258 reg = <0x120000 0x1000 0x121000 0x1000>; 259 }; 260 dcsr-cpu-sb-proxy@128000 { 261 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 262 cpu-handle = <&cpu5>; 263 reg = <0x128000 0x1000 0x129000 0x1000>; 264 }; 265 dcsr-cpu-sb-proxy@130000 { 266 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 267 cpu-handle = <&cpu6>; 268 reg = <0x130000 0x1000 0x131000 0x1000>; 269 }; 270 dcsr-cpu-sb-proxy@138000 { 271 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 272 cpu-handle = <&cpu7>; 273 reg = <0x138000 0x1000 0x139000 0x1000>; 274 }; 275 dcsr-cpu-sb-proxy@140000 { 276 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 277 cpu-handle = <&cpu8>; 278 reg = <0x140000 0x1000 0x141000 0x1000>; 279 }; 280 dcsr-cpu-sb-proxy@148000 { 281 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 282 cpu-handle = <&cpu9>; 283 reg = <0x148000 0x1000 0x149000 0x1000>; 284 }; 285 dcsr-cpu-sb-proxy@150000 { 286 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 287 cpu-handle = <&cpu10>; 288 reg = <0x150000 0x1000 0x151000 0x1000>; 289 }; 290 dcsr-cpu-sb-proxy@158000 { 291 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 292 cpu-handle = <&cpu11>; 293 reg = <0x158000 0x1000 0x159000 0x1000>; 294 }; 295}; 296 297&soc { 298 #address-cells = <1>; 299 #size-cells = <1>; 300 device_type = "soc"; 301 compatible = "simple-bus"; 302 303 soc-sram-error { 304 compatible = "fsl,soc-sram-error"; 305 interrupts = <16 2 1 29>; 306 }; 307 308 corenet-law@0 { 309 compatible = "fsl,corenet-law"; 310 reg = <0x0 0x1000>; 311 fsl,num-laws = <32>; 312 }; 313 314 ddr1: memory-controller@8000 { 315 compatible = "fsl,qoriq-memory-controller-v4.7", 316 "fsl,qoriq-memory-controller"; 317 reg = <0x8000 0x1000>; 318 interrupts = <16 2 1 23>; 319 }; 320 321 ddr2: memory-controller@9000 { 322 compatible = "fsl,qoriq-memory-controller-v4.7", 323 "fsl,qoriq-memory-controller"; 324 reg = <0x9000 0x1000>; 325 interrupts = <16 2 1 22>; 326 }; 327 328 ddr3: memory-controller@a000 { 329 compatible = "fsl,qoriq-memory-controller-v4.7", 330 "fsl,qoriq-memory-controller"; 331 reg = <0xa000 0x1000>; 332 interrupts = <16 2 1 21>; 333 }; 334 335 cpc: l3-cache-controller@10000 { 336 compatible = "fsl,t4240-l3-cache-controller", "cache"; 337 reg = <0x10000 0x1000 338 0x11000 0x1000 339 0x12000 0x1000>; 340 interrupts = <16 2 1 27 341 16 2 1 26 342 16 2 1 25>; 343 }; 344 345 corenet-cf@18000 { 346 compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; 347 reg = <0x18000 0x1000>; 348 interrupts = <16 2 1 31>; 349 fsl,ccf-num-csdids = <32>; 350 fsl,ccf-num-snoopids = <32>; 351 }; 352 353 iommu@20000 { 354 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 355 reg = <0x20000 0x6000>; 356 fsl,portid-mapping = <0x8000>; 357 interrupts = < 358 24 2 0 0 359 16 2 1 30>; 360 }; 361 362/include/ "qoriq-mpic4.3.dtsi" 363 364 guts: global-utilities@e0000 { 365 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0"; 366 reg = <0xe0000 0xe00>; 367 fsl,has-rstcr; 368 fsl,liodn-bits = <12>; 369 }; 370 371 clockgen: global-utilities@e1000 { 372 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 373 ranges = <0x0 0xe1000 0x1000>; 374 reg = <0xe1000 0x1000>; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 378 sysclk: sysclk { 379 #clock-cells = <0>; 380 compatible = "fsl,qoriq-sysclk-2.0"; 381 clock-output-names = "sysclk"; 382 }; 383 384 pll0: pll0@800 { 385 #clock-cells = <1>; 386 reg = <0x800 0x4>; 387 compatible = "fsl,qoriq-core-pll-2.0"; 388 clocks = <&sysclk>; 389 clock-output-names = "pll0", "pll0-div2", "pll0-div4"; 390 }; 391 392 pll1: pll1@820 { 393 #clock-cells = <1>; 394 reg = <0x820 0x4>; 395 compatible = "fsl,qoriq-core-pll-2.0"; 396 clocks = <&sysclk>; 397 clock-output-names = "pll1", "pll1-div2", "pll1-div4"; 398 }; 399 400 pll2: pll2@840 { 401 #clock-cells = <1>; 402 reg = <0x840 0x4>; 403 compatible = "fsl,qoriq-core-pll-2.0"; 404 clocks = <&sysclk>; 405 clock-output-names = "pll2", "pll2-div2", "pll2-div4"; 406 }; 407 408 pll3: pll3@860 { 409 #clock-cells = <1>; 410 reg = <0x860 0x4>; 411 compatible = "fsl,qoriq-core-pll-2.0"; 412 clocks = <&sysclk>; 413 clock-output-names = "pll3", "pll3-div2", "pll3-div4"; 414 }; 415 416 pll4: pll4@880 { 417 #clock-cells = <1>; 418 reg = <0x880 0x4>; 419 compatible = "fsl,qoriq-core-pll-2.0"; 420 clocks = <&sysclk>; 421 clock-output-names = "pll4", "pll4-div2", "pll4-div4"; 422 }; 423 424 mux0: mux0@0 { 425 #clock-cells = <0>; 426 reg = <0x0 0x4>; 427 compatible = "fsl,qoriq-core-mux-2.0"; 428 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 429 <&pll1 0>, <&pll1 1>, <&pll1 2>, 430 <&pll2 0>, <&pll2 1>, <&pll2 2>; 431 clock-names = "pll0", "pll0-div2", "pll0-div4", 432 "pll1", "pll1-div2", "pll1-div4", 433 "pll2", "pll2-div2", "pll2-div4"; 434 clock-output-names = "cmux0"; 435 }; 436 437 mux1: mux1@20 { 438 #clock-cells = <0>; 439 reg = <0x20 0x4>; 440 compatible = "fsl,qoriq-core-mux-2.0"; 441 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 442 <&pll1 0>, <&pll1 1>, <&pll1 2>, 443 <&pll2 0>, <&pll2 1>, <&pll2 2>; 444 clock-names = "pll0", "pll0-div2", "pll0-div4", 445 "pll1", "pll1-div2", "pll1-div4", 446 "pll2", "pll2-div2", "pll2-div4"; 447 clock-output-names = "cmux1"; 448 }; 449 450 mux2: mux2@40 { 451 #clock-cells = <0>; 452 reg = <0x40 0x4>; 453 compatible = "fsl,qoriq-core-mux-2.0"; 454 clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, 455 <&pll4 0>, <&pll4 1>, <&pll4 2>; 456 clock-names = "pll3", "pll3-div2", "pll3-div4", 457 "pll4", "pll4-div2", "pll4-div4"; 458 clock-output-names = "cmux2"; 459 }; 460 }; 461 462 rcpm: global-utilities@e2000 { 463 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; 464 reg = <0xe2000 0x1000>; 465 }; 466 467 sfp: sfp@e8000 { 468 compatible = "fsl,t4240-sfp"; 469 reg = <0xe8000 0x1000>; 470 }; 471 472 serdes: serdes@ea000 { 473 compatible = "fsl,t4240-serdes"; 474 reg = <0xea000 0x4000>; 475 }; 476 477/include/ "elo3-dma-0.dtsi" 478/include/ "elo3-dma-1.dtsi" 479/include/ "elo3-dma-2.dtsi" 480 481/include/ "qoriq-espi-0.dtsi" 482 spi@110000 { 483 fsl,espi-num-chipselects = <4>; 484 }; 485 486/include/ "qoriq-esdhc-0.dtsi" 487 sdhc@114000 { 488 compatible = "fsl,t4240-esdhc", "fsl,esdhc"; 489 sdhci,auto-cmd12; 490 }; 491/include/ "qoriq-i2c-0.dtsi" 492/include/ "qoriq-i2c-1.dtsi" 493/include/ "qoriq-duart-0.dtsi" 494/include/ "qoriq-duart-1.dtsi" 495/include/ "qoriq-gpio-0.dtsi" 496/include/ "qoriq-gpio-1.dtsi" 497/include/ "qoriq-gpio-2.dtsi" 498/include/ "qoriq-gpio-3.dtsi" 499/include/ "qoriq-usb2-mph-0.dtsi" 500 usb0: usb@210000 { 501 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; 502 phy_type = "utmi"; 503 port0; 504 }; 505/include/ "qoriq-usb2-dr-0.dtsi" 506 usb1: usb@211000 { 507 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 508 dr_mode = "host"; 509 phy_type = "utmi"; 510 }; 511/include/ "qoriq-sata2-0.dtsi" 512/include/ "qoriq-sata2-1.dtsi" 513/include/ "qoriq-sec5.0-0.dtsi" 514 515 L2_1: l2-cache-controller@c20000 { 516 compatible = "fsl,t4240-l2-cache-controller"; 517 reg = <0xc20000 0x40000>; 518 next-level-cache = <&cpc>; 519 }; 520 L2_2: l2-cache-controller@c60000 { 521 compatible = "fsl,t4240-l2-cache-controller"; 522 reg = <0xc60000 0x40000>; 523 next-level-cache = <&cpc>; 524 }; 525 L2_3: l2-cache-controller@ca0000 { 526 compatible = "fsl,t4240-l2-cache-controller"; 527 reg = <0xca0000 0x40000>; 528 next-level-cache = <&cpc>; 529 }; 530}; 531