1/*
2 * T2080/T2081 QDS Device Tree Source
3 *
4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36	model = "fsl,T2080QDS";
37	compatible = "fsl,T2080QDS";
38	#address-cells = <2>;
39	#size-cells = <2>;
40	interrupt-parent = <&mpic>;
41
42	reserved-memory {
43		#address-cells = <2>;
44		#size-cells = <2>;
45		ranges;
46
47		bman_fbpr: bman-fbpr {
48			size = <0 0x1000000>;
49			alignment = <0 0x1000000>;
50		};
51		qman_fqd: qman-fqd {
52			size = <0 0x400000>;
53			alignment = <0 0x400000>;
54		};
55		qman_pfdr: qman-pfdr {
56			size = <0 0x2000000>;
57			alignment = <0 0x2000000>;
58		};
59	};
60
61	ifc: localbus@ffe124000 {
62		reg = <0xf 0xfe124000 0 0x2000>;
63		ranges = <0 0 0xf 0xe8000000 0x08000000
64			  2 0 0xf 0xff800000 0x00010000
65			  3 0 0xf 0xffdf0000 0x00008000>;
66
67		nor@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x8000000>;
72			bank-width = <2>;
73			device-width = <1>;
74		};
75
76		nand@2,0 {
77			#address-cells = <1>;
78			#size-cells = <1>;
79			compatible = "fsl,ifc-nand";
80			reg = <0x2 0x0 0x10000>;
81		};
82
83		boardctrl: board-control@3,0 {
84			#address-cells = <1>;
85			#size-cells = <1>;
86			compatible = "fsl,fpga-qixis";
87			reg = <3 0 0x300>;
88			ranges = <0 3 0 0x300>;
89		};
90	};
91
92	memory {
93		device_type = "memory";
94	};
95
96	dcsr: dcsr@f00000000 {
97		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
98	};
99
100	bportals: bman-portals@ff4000000 {
101		ranges = <0x0 0xf 0xf4000000 0x2000000>;
102	};
103
104	qportals: qman-portals@ff6000000 {
105		ranges = <0x0 0xf 0xf6000000 0x2000000>;
106	};
107
108	soc: soc@ffe000000 {
109		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
110		reg = <0xf 0xfe000000 0 0x00001000>;
111		spi@110000 {
112			flash@0 {
113				#address-cells = <1>;
114				#size-cells = <1>;
115				compatible = "micron,n25q128a11"; /* 16MB */
116				reg = <0>;
117				spi-max-frequency = <40000000>; /* input clock */
118			};
119
120			flash@1 {
121				#address-cells = <1>;
122				#size-cells = <1>;
123				compatible = "sst,sst25wf040";
124				reg = <1>;
125				spi-max-frequency = <35000000>;
126			};
127
128			flash@2 {
129				#address-cells = <1>;
130				#size-cells = <1>;
131				compatible = "eon,en25s64";
132				reg = <2>;
133				spi-max-frequency = <35000000>;
134			};
135		};
136
137		i2c@118000 {
138			pca9547@77 {
139				compatible = "nxp,pca9547";
140				reg = <0x77>;
141				#address-cells = <1>;
142				#size-cells = <0>;
143
144				i2c@0 {
145					#address-cells = <1>;
146					#size-cells = <0>;
147					reg = <0x0>;
148
149					eeprom@50 {
150						compatible = "at24,24c512";
151						reg = <0x50>;
152					};
153
154					eeprom@51 {
155						compatible = "at24,24c02";
156						reg = <0x51>;
157					};
158
159					eeprom@57 {
160						compatible = "at24,24c02";
161						reg = <0x57>;
162					};
163
164					rtc@68 {
165						compatible = "dallas,ds3232";
166						reg = <0x68>;
167						interrupts = <0xb 0x1 0 0>;
168					};
169				};
170
171				i2c@1 {
172					#address-cells = <1>;
173					#size-cells = <0>;
174					reg = <0x1>;
175
176					eeprom@55 {
177						compatible = "at24,24c02";
178						reg = <0x55>;
179					};
180				};
181
182				i2c@2 {
183					#address-cells = <1>;
184					#size-cells = <0>;
185					reg = <0x2>;
186
187					ina220@40 {
188						compatible = "ti,ina220";
189						reg = <0x40>;
190						shunt-resistor = <1000>;
191					};
192
193					ina220@41 {
194						compatible = "ti,ina220";
195						reg = <0x41>;
196						shunt-resistor = <1000>;
197					};
198				};
199
200				i2c@3 {
201					#address-cells = <1>;
202					#size-cells = <0>;
203					reg = <0x3>;
204
205					adt7461@4c {
206						compatible = "adi,adt7461";
207						reg = <0x4c>;
208					};
209				};
210			};
211		};
212
213		sdhc@114000 {
214			voltage-ranges = <1800 1800 3300 3300>;
215		};
216	};
217
218	pci0: pcie@ffe240000 {
219		reg = <0xf 0xfe240000 0 0x10000>;
220		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
221			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
222		pcie@0 {
223			ranges = <0x02000000 0 0xe0000000
224				  0x02000000 0 0xe0000000
225				  0 0x20000000
226
227				  0x01000000 0 0x00000000
228				  0x01000000 0 0x00000000
229				  0 0x00010000>;
230		};
231	};
232
233	pci1: pcie@ffe250000 {
234		reg = <0xf 0xfe250000 0 0x10000>;
235		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
236			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
237		pcie@0 {
238			ranges = <0x02000000 0 0xe0000000
239				  0x02000000 0 0xe0000000
240				  0 0x20000000
241
242				  0x01000000 0 0x00000000
243				  0x01000000 0 0x00000000
244				  0 0x00010000>;
245		};
246	};
247
248	pci2: pcie@ffe260000 {
249		reg = <0xf 0xfe260000 0 0x1000>;
250		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
251			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
252		pcie@0 {
253			ranges = <0x02000000 0 0xe0000000
254				  0x02000000 0 0xe0000000
255				  0 0x20000000
256
257				  0x01000000 0 0x00000000
258				  0x01000000 0 0x00000000
259				  0 0x00010000>;
260		};
261	};
262
263	pci3: pcie@ffe270000 {
264		reg = <0xf 0xfe270000 0 0x10000>;
265		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
266			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
267		pcie@0 {
268			ranges = <0x02000000 0 0xe0000000
269				  0x02000000 0 0xe0000000
270				  0 0x20000000
271
272				  0x01000000 0 0x00000000
273				  0x01000000 0 0x00000000
274				  0 0x00010000>;
275		};
276	};
277};
278