1/* 2 * T1040 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2013 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&ifc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,ifc", "simple-bus"; 39 interrupts = <25 2 0 0>; 40}; 41 42&pci0 { 43 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 44 device_type = "pci"; 45 #size-cells = <2>; 46 #address-cells = <3>; 47 bus-range = <0x0 0xff>; 48 interrupts = <20 2 0 0>; 49 fsl,iommu-parent = <&pamu0>; 50 pcie@0 { 51 reg = <0 0 0 0 0>; 52 #interrupt-cells = <1>; 53 #size-cells = <2>; 54 #address-cells = <3>; 55 device_type = "pci"; 56 interrupts = <20 2 0 0>; 57 interrupt-map-mask = <0xf800 0 0 7>; 58 interrupt-map = < 59 /* IDSEL 0x0 */ 60 0000 0 0 1 &mpic 40 1 0 0 61 0000 0 0 2 &mpic 1 1 0 0 62 0000 0 0 3 &mpic 2 1 0 0 63 0000 0 0 4 &mpic 3 1 0 0 64 >; 65 }; 66}; 67 68&pci1 { 69 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 70 device_type = "pci"; 71 #size-cells = <2>; 72 #address-cells = <3>; 73 bus-range = <0 0xff>; 74 interrupts = <21 2 0 0>; 75 fsl,iommu-parent = <&pamu0>; 76 pcie@0 { 77 reg = <0 0 0 0 0>; 78 #interrupt-cells = <1>; 79 #size-cells = <2>; 80 #address-cells = <3>; 81 device_type = "pci"; 82 interrupts = <21 2 0 0>; 83 interrupt-map-mask = <0xf800 0 0 7>; 84 interrupt-map = < 85 /* IDSEL 0x0 */ 86 0000 0 0 1 &mpic 41 1 0 0 87 0000 0 0 2 &mpic 5 1 0 0 88 0000 0 0 3 &mpic 6 1 0 0 89 0000 0 0 4 &mpic 7 1 0 0 90 >; 91 }; 92}; 93 94&pci2 { 95 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 96 device_type = "pci"; 97 #size-cells = <2>; 98 #address-cells = <3>; 99 bus-range = <0x0 0xff>; 100 interrupts = <22 2 0 0>; 101 fsl,iommu-parent = <&pamu0>; 102 pcie@0 { 103 reg = <0 0 0 0 0>; 104 #interrupt-cells = <1>; 105 #size-cells = <2>; 106 #address-cells = <3>; 107 device_type = "pci"; 108 interrupts = <22 2 0 0>; 109 interrupt-map-mask = <0xf800 0 0 7>; 110 interrupt-map = < 111 /* IDSEL 0x0 */ 112 0000 0 0 1 &mpic 42 1 0 0 113 0000 0 0 2 &mpic 9 1 0 0 114 0000 0 0 3 &mpic 10 1 0 0 115 0000 0 0 4 &mpic 11 1 0 0 116 >; 117 }; 118}; 119 120&pci3 { 121 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; 122 device_type = "pci"; 123 #size-cells = <2>; 124 #address-cells = <3>; 125 bus-range = <0x0 0xff>; 126 interrupts = <23 2 0 0>; 127 fsl,iommu-parent = <&pamu0>; 128 pcie@0 { 129 reg = <0 0 0 0 0>; 130 #interrupt-cells = <1>; 131 #size-cells = <2>; 132 #address-cells = <3>; 133 device_type = "pci"; 134 interrupts = <23 2 0 0>; 135 interrupt-map-mask = <0xf800 0 0 7>; 136 interrupt-map = < 137 /* IDSEL 0x0 */ 138 0000 0 0 1 &mpic 43 1 0 0 139 0000 0 0 2 &mpic 0 1 0 0 140 0000 0 0 3 &mpic 4 1 0 0 141 0000 0 0 4 &mpic 8 1 0 0 142 >; 143 }; 144}; 145 146&dcsr { 147 #address-cells = <1>; 148 #size-cells = <1>; 149 compatible = "fsl,dcsr", "simple-bus"; 150 151 dcsr-epu@0 { 152 compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu"; 153 interrupts = <52 2 0 0 154 84 2 0 0 155 85 2 0 0>; 156 reg = <0x0 0x1000>; 157 }; 158 dcsr-npc { 159 compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc"; 160 reg = <0x1000 0x1000 0x1002000 0x10000>; 161 }; 162 dcsr-nxc@2000 { 163 compatible = "fsl,dcsr-nxc"; 164 reg = <0x2000 0x1000>; 165 }; 166 dcsr-corenet { 167 compatible = "fsl,dcsr-corenet"; 168 reg = <0x8000 0x1000 0x1A000 0x1000>; 169 }; 170 dcsr-dpaa@9000 { 171 compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa"; 172 reg = <0x9000 0x1000>; 173 }; 174 dcsr-ocn@11000 { 175 compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn"; 176 reg = <0x11000 0x1000>; 177 }; 178 dcsr-ddr@12000 { 179 compatible = "fsl,dcsr-ddr"; 180 dev-handle = <&ddr1>; 181 reg = <0x12000 0x1000>; 182 }; 183 dcsr-nal@18000 { 184 compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal"; 185 reg = <0x18000 0x1000>; 186 }; 187 dcsr-rcpm@22000 { 188 compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm"; 189 reg = <0x22000 0x1000>; 190 }; 191 dcsr-snpc@30000 { 192 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; 193 reg = <0x30000 0x1000 0x1022000 0x10000>; 194 }; 195 dcsr-snpc@31000 { 196 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc"; 197 reg = <0x31000 0x1000 0x1042000 0x10000>; 198 }; 199 dcsr-cpu-sb-proxy@100000 { 200 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 201 cpu-handle = <&cpu0>; 202 reg = <0x100000 0x1000 0x101000 0x1000>; 203 }; 204 dcsr-cpu-sb-proxy@108000 { 205 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 206 cpu-handle = <&cpu1>; 207 reg = <0x108000 0x1000 0x109000 0x1000>; 208 }; 209 dcsr-cpu-sb-proxy@110000 { 210 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 211 cpu-handle = <&cpu2>; 212 reg = <0x110000 0x1000 0x111000 0x1000>; 213 }; 214 dcsr-cpu-sb-proxy@118000 { 215 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 216 cpu-handle = <&cpu3>; 217 reg = <0x118000 0x1000 0x119000 0x1000>; 218 }; 219}; 220 221&soc { 222 #address-cells = <1>; 223 #size-cells = <1>; 224 device_type = "soc"; 225 compatible = "simple-bus"; 226 227 soc-sram-error { 228 compatible = "fsl,soc-sram-error"; 229 interrupts = <16 2 1 29>; 230 }; 231 232 corenet-law@0 { 233 compatible = "fsl,corenet-law"; 234 reg = <0x0 0x1000>; 235 fsl,num-laws = <16>; 236 }; 237 238 ddr1: memory-controller@8000 { 239 compatible = "fsl,qoriq-memory-controller-v5.0", 240 "fsl,qoriq-memory-controller"; 241 reg = <0x8000 0x1000>; 242 interrupts = <16 2 1 23>; 243 }; 244 245 cpc: l3-cache-controller@10000 { 246 compatible = "fsl,t1040-l3-cache-controller", "cache"; 247 reg = <0x10000 0x1000>; 248 interrupts = <16 2 1 27>; 249 }; 250 251 corenet-cf@18000 { 252 compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; 253 reg = <0x18000 0x1000>; 254 interrupts = <16 2 1 31>; 255 fsl,ccf-num-csdids = <32>; 256 fsl,ccf-num-snoopids = <32>; 257 }; 258 259 iommu@20000 { 260 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 261 reg = <0x20000 0x1000>; 262 ranges = <0 0x20000 0x1000>; 263 #address-cells = <1>; 264 #size-cells = <1>; 265 interrupts = < 266 24 2 0 0 267 16 2 1 30>; 268 pamu0: pamu@0 { 269 reg = <0 0x1000>; 270 fsl,primary-cache-geometry = <128 1>; 271 fsl,secondary-cache-geometry = <16 2>; 272 }; 273 }; 274 275/include/ "qoriq-mpic.dtsi" 276 277 guts: global-utilities@e0000 { 278 compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0"; 279 reg = <0xe0000 0xe00>; 280 fsl,has-rstcr; 281 fsl,liodn-bits = <12>; 282 }; 283 284/include/ "qoriq-clockgen2.dtsi" 285 global-utilities@e1000 { 286 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; 287 288 mux0: mux0@0 { 289 #clock-cells = <0>; 290 reg = <0x0 4>; 291 compatible = "fsl,qoriq-core-mux-2.0"; 292 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 293 <&pll1 0>, <&pll1 1>, <&pll1 2>; 294 clock-names = "pll0", "pll0-div2", "pll1-div4", 295 "pll1", "pll1-div2", "pll1-div4"; 296 clock-output-names = "cmux0"; 297 }; 298 299 mux1: mux1@20 { 300 #clock-cells = <0>; 301 reg = <0x20 4>; 302 compatible = "fsl,qoriq-core-mux-2.0"; 303 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 304 <&pll1 0>, <&pll1 1>, <&pll1 2>; 305 clock-names = "pll0", "pll0-div2", "pll1-div4", 306 "pll1", "pll1-div2", "pll1-div4"; 307 clock-output-names = "cmux1"; 308 }; 309 310 mux2: mux2@40 { 311 #clock-cells = <0>; 312 reg = <0x40 4>; 313 compatible = "fsl,qoriq-core-mux-2.0"; 314 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 315 <&pll1 0>, <&pll1 1>, <&pll1 2>; 316 clock-names = "pll0", "pll0-div2", "pll1-div4", 317 "pll1", "pll1-div2", "pll1-div4"; 318 clock-output-names = "cmux2"; 319 }; 320 321 mux3: mux3@60 { 322 #clock-cells = <0>; 323 reg = <0x60 4>; 324 compatible = "fsl,qoriq-core-mux-2.0"; 325 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 326 <&pll1 0>, <&pll1 1>, <&pll1 2>; 327 clock-names = "pll0_0", "pll0_1", "pll0_2", 328 "pll1_0", "pll1_1", "pll1_2"; 329 clock-output-names = "cmux3"; 330 }; 331 }; 332 333 rcpm: global-utilities@e2000 { 334 compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0"; 335 reg = <0xe2000 0x1000>; 336 }; 337 338 sfp: sfp@e8000 { 339 compatible = "fsl,t1040-sfp"; 340 reg = <0xe8000 0x1000>; 341 }; 342 343 serdes: serdes@ea000 { 344 compatible = "fsl,t1040-serdes"; 345 reg = <0xea000 0x4000>; 346 }; 347 348/include/ "elo3-dma-0.dtsi" 349/include/ "elo3-dma-1.dtsi" 350/include/ "qoriq-espi-0.dtsi" 351 spi@110000 { 352 fsl,espi-num-chipselects = <4>; 353 }; 354 355/include/ "qoriq-esdhc-0.dtsi" 356 sdhc@114000 { 357 compatible = "fsl,t1040-esdhc", "fsl,esdhc"; 358 fsl,iommu-parent = <&pamu0>; 359 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 360 sdhci,auto-cmd12; 361 }; 362/include/ "qoriq-i2c-0.dtsi" 363/include/ "qoriq-i2c-1.dtsi" 364/include/ "qoriq-duart-0.dtsi" 365/include/ "qoriq-duart-1.dtsi" 366/include/ "qoriq-gpio-0.dtsi" 367/include/ "qoriq-gpio-1.dtsi" 368/include/ "qoriq-gpio-2.dtsi" 369/include/ "qoriq-gpio-3.dtsi" 370/include/ "qoriq-usb2-mph-0.dtsi" 371 usb0: usb@210000 { 372 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; 373 fsl,iommu-parent = <&pamu0>; 374 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 375 phy_type = "utmi"; 376 port0; 377 }; 378/include/ "qoriq-usb2-dr-0.dtsi" 379 usb1: usb@211000 { 380 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 381 fsl,iommu-parent = <&pamu0>; 382 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ 383 dr_mode = "host"; 384 phy_type = "utmi"; 385 }; 386 387 display@180000 { 388 compatible = "fsl,t1040-diu", "fsl,diu"; 389 reg = <0x180000 1000>; 390 interrupts = <74 2 0 0>; 391 }; 392 393/include/ "qoriq-sata2-0.dtsi" 394 sata@220000 { 395 fsl,iommu-parent = <&pamu0>; 396 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ 397 }; 398/include/ "qoriq-sata2-1.dtsi" 399 sata@221000 { 400 fsl,iommu-parent = <&pamu0>; 401 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ 402 }; 403/include/ "qoriq-sec5.0-0.dtsi" 404}; 405