1eaffcb0fSEmil Medve/* 2eaffcb0fSEmil Medve * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ] 3eaffcb0fSEmil Medve * 4eaffcb0fSEmil Medve * Copyright 2014 Freescale Semiconductor Inc. 5eaffcb0fSEmil Medve * 6eaffcb0fSEmil Medve * Redistribution and use in source and binary forms, with or without 7eaffcb0fSEmil Medve * modification, are permitted provided that the following conditions are met: 8eaffcb0fSEmil Medve * * Redistributions of source code must retain the above copyright 9eaffcb0fSEmil Medve * notice, this list of conditions and the following disclaimer. 10eaffcb0fSEmil Medve * * Redistributions in binary form must reproduce the above copyright 11eaffcb0fSEmil Medve * notice, this list of conditions and the following disclaimer in the 12eaffcb0fSEmil Medve * documentation and/or other materials provided with the distribution. 13eaffcb0fSEmil Medve * * Neither the name of Freescale Semiconductor nor the 14eaffcb0fSEmil Medve * names of its contributors may be used to endorse or promote products 15eaffcb0fSEmil Medve * derived from this software without specific prior written permission. 16eaffcb0fSEmil Medve * 17eaffcb0fSEmil Medve * 18eaffcb0fSEmil Medve * ALTERNATIVELY, this software may be distributed under the terms of the 19eaffcb0fSEmil Medve * GNU General Public License ("GPL") as published by the Free Software 20eaffcb0fSEmil Medve * Foundation, either version 2 of that License or (at your option) any 21eaffcb0fSEmil Medve * later version. 22eaffcb0fSEmil Medve * 23eaffcb0fSEmil Medve * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24eaffcb0fSEmil Medve * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25eaffcb0fSEmil Medve * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26eaffcb0fSEmil Medve * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27eaffcb0fSEmil Medve * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28eaffcb0fSEmil Medve * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29eaffcb0fSEmil Medve * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30eaffcb0fSEmil Medve * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31eaffcb0fSEmil Medve * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32eaffcb0fSEmil Medve * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33eaffcb0fSEmil Medve */ 34eaffcb0fSEmil Medve 35eaffcb0fSEmil Medveglobal-utilities@e1000 { 36eaffcb0fSEmil Medve compatible = "fsl,qoriq-clockgen-1.0"; 37eaffcb0fSEmil Medve ranges = <0x0 0xe1000 0x1000>; 38eaffcb0fSEmil Medve reg = <0xe1000 0x1000>; 39eaffcb0fSEmil Medve clock-frequency = <0>; 40eaffcb0fSEmil Medve #address-cells = <1>; 41eaffcb0fSEmil Medve #size-cells = <1>; 42eaffcb0fSEmil Medve 43eaffcb0fSEmil Medve sysclk: sysclk { 44eaffcb0fSEmil Medve #clock-cells = <0>; 45eaffcb0fSEmil Medve compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock"; 46eaffcb0fSEmil Medve clock-output-names = "sysclk"; 47eaffcb0fSEmil Medve }; 48eaffcb0fSEmil Medve pll0: pll0@800 { 49eaffcb0fSEmil Medve #clock-cells = <1>; 50eaffcb0fSEmil Medve reg = <0x800 0x4>; 51eaffcb0fSEmil Medve compatible = "fsl,qoriq-core-pll-1.0"; 52eaffcb0fSEmil Medve clocks = <&sysclk>; 53eaffcb0fSEmil Medve clock-output-names = "pll0", "pll0-div2"; 54eaffcb0fSEmil Medve }; 55eaffcb0fSEmil Medve pll1: pll1@820 { 56eaffcb0fSEmil Medve #clock-cells = <1>; 57eaffcb0fSEmil Medve reg = <0x820 0x4>; 58eaffcb0fSEmil Medve compatible = "fsl,qoriq-core-pll-1.0"; 59eaffcb0fSEmil Medve clocks = <&sysclk>; 60eaffcb0fSEmil Medve clock-output-names = "pll1", "pll1-div2"; 61eaffcb0fSEmil Medve }; 62eaffcb0fSEmil Medve mux0: mux0@0 { 63eaffcb0fSEmil Medve #clock-cells = <0>; 64eaffcb0fSEmil Medve reg = <0x0 0x4>; 65eaffcb0fSEmil Medve compatible = "fsl,qoriq-core-mux-1.0"; 66eaffcb0fSEmil Medve clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 67eaffcb0fSEmil Medve clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 68eaffcb0fSEmil Medve clock-output-names = "cmux0"; 69eaffcb0fSEmil Medve }; 70eaffcb0fSEmil Medve mux1: mux1@20 { 71eaffcb0fSEmil Medve #clock-cells = <0>; 72eaffcb0fSEmil Medve reg = <0x20 0x4>; 73eaffcb0fSEmil Medve compatible = "fsl,qoriq-core-mux-1.0"; 74eaffcb0fSEmil Medve clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 75eaffcb0fSEmil Medve clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 76eaffcb0fSEmil Medve clock-output-names = "cmux1"; 77eaffcb0fSEmil Medve }; 78eaffcb0fSEmil Medve}; 79