1/* 2 * P5020/5010 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; 37 interrupts = <25 2 0 0>; 38 #address-cells = <2>; 39 #size-cells = <1>; 40}; 41 42/* controller at 0x200000 */ 43&pci0 { 44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 clock-frequency = <33333333>; 50 interrupts = <16 2 1 15>; 51 pcie@0 { 52 reg = <0 0 0 0 0>; 53 #interrupt-cells = <1>; 54 #size-cells = <2>; 55 #address-cells = <3>; 56 device_type = "pci"; 57 interrupts = <16 2 1 15>; 58 interrupt-map-mask = <0xf800 0 0 7>; 59 interrupt-map = < 60 /* IDSEL 0x0 */ 61 0000 0 0 1 &mpic 40 1 0 0 62 0000 0 0 2 &mpic 1 1 0 0 63 0000 0 0 3 &mpic 2 1 0 0 64 0000 0 0 4 &mpic 3 1 0 0 65 >; 66 }; 67}; 68 69/* controller at 0x201000 */ 70&pci1 { 71 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 72 device_type = "pci"; 73 #size-cells = <2>; 74 #address-cells = <3>; 75 bus-range = <0 0xff>; 76 clock-frequency = <33333333>; 77 interrupts = <16 2 1 14>; 78 pcie@0 { 79 reg = <0 0 0 0 0>; 80 #interrupt-cells = <1>; 81 #size-cells = <2>; 82 #address-cells = <3>; 83 device_type = "pci"; 84 interrupts = <16 2 1 14>; 85 interrupt-map-mask = <0xf800 0 0 7>; 86 interrupt-map = < 87 /* IDSEL 0x0 */ 88 0000 0 0 1 &mpic 41 1 0 0 89 0000 0 0 2 &mpic 5 1 0 0 90 0000 0 0 3 &mpic 6 1 0 0 91 0000 0 0 4 &mpic 7 1 0 0 92 >; 93 }; 94}; 95 96/* controller at 0x202000 */ 97&pci2 { 98 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 99 device_type = "pci"; 100 #size-cells = <2>; 101 #address-cells = <3>; 102 bus-range = <0x0 0xff>; 103 clock-frequency = <33333333>; 104 interrupts = <16 2 1 13>; 105 pcie@0 { 106 reg = <0 0 0 0 0>; 107 #interrupt-cells = <1>; 108 #size-cells = <2>; 109 #address-cells = <3>; 110 device_type = "pci"; 111 interrupts = <16 2 1 13>; 112 interrupt-map-mask = <0xf800 0 0 7>; 113 interrupt-map = < 114 /* IDSEL 0x0 */ 115 0000 0 0 1 &mpic 42 1 0 0 116 0000 0 0 2 &mpic 9 1 0 0 117 0000 0 0 3 &mpic 10 1 0 0 118 0000 0 0 4 &mpic 11 1 0 0 119 >; 120 }; 121}; 122 123/* controller at 0x203000 */ 124&pci3 { 125 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 126 device_type = "pci"; 127 #size-cells = <2>; 128 #address-cells = <3>; 129 bus-range = <0x0 0xff>; 130 clock-frequency = <33333333>; 131 interrupts = <16 2 1 12>; 132 pcie@0 { 133 reg = <0 0 0 0 0>; 134 #interrupt-cells = <1>; 135 #size-cells = <2>; 136 #address-cells = <3>; 137 device_type = "pci"; 138 interrupts = <16 2 1 12>; 139 interrupt-map-mask = <0xf800 0 0 7>; 140 interrupt-map = < 141 /* IDSEL 0x0 */ 142 0000 0 0 1 &mpic 43 1 0 0 143 0000 0 0 2 &mpic 0 1 0 0 144 0000 0 0 3 &mpic 4 1 0 0 145 0000 0 0 4 &mpic 8 1 0 0 146 >; 147 }; 148}; 149 150&dcsr { 151 #address-cells = <1>; 152 #size-cells = <1>; 153 compatible = "fsl,dcsr", "simple-bus"; 154 155 dcsr-epu@0 { 156 compatible = "fsl,dcsr-epu"; 157 interrupts = <52 2 0 0 158 84 2 0 0 159 85 2 0 0>; 160 reg = <0x0 0x1000>; 161 }; 162 dcsr-npc { 163 compatible = "fsl,dcsr-npc"; 164 reg = <0x1000 0x1000 0x1000000 0x8000>; 165 }; 166 dcsr-nxc@2000 { 167 compatible = "fsl,dcsr-nxc"; 168 reg = <0x2000 0x1000>; 169 }; 170 dcsr-corenet { 171 compatible = "fsl,dcsr-corenet"; 172 reg = <0x8000 0x1000 0xB0000 0x1000>; 173 }; 174 dcsr-dpaa@9000 { 175 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa"; 176 reg = <0x9000 0x1000>; 177 }; 178 dcsr-ocn@11000 { 179 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn"; 180 reg = <0x11000 0x1000>; 181 }; 182 dcsr-ddr@12000 { 183 compatible = "fsl,dcsr-ddr"; 184 dev-handle = <&ddr1>; 185 reg = <0x12000 0x1000>; 186 }; 187 dcsr-ddr@13000 { 188 compatible = "fsl,dcsr-ddr"; 189 dev-handle = <&ddr2>; 190 reg = <0x13000 0x1000>; 191 }; 192 dcsr-nal@18000 { 193 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal"; 194 reg = <0x18000 0x1000>; 195 }; 196 dcsr-rcpm@22000 { 197 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm"; 198 reg = <0x22000 0x1000>; 199 }; 200 dcsr-cpu-sb-proxy@40000 { 201 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 202 cpu-handle = <&cpu0>; 203 reg = <0x40000 0x1000>; 204 }; 205 dcsr-cpu-sb-proxy@41000 { 206 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 207 cpu-handle = <&cpu1>; 208 reg = <0x41000 0x1000>; 209 }; 210}; 211 212&soc { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 device_type = "soc"; 216 compatible = "simple-bus"; 217 218 soc-sram-error { 219 compatible = "fsl,soc-sram-error"; 220 interrupts = <16 2 1 29>; 221 }; 222 223 corenet-law@0 { 224 compatible = "fsl,corenet-law"; 225 reg = <0x0 0x1000>; 226 fsl,num-laws = <32>; 227 }; 228 229 ddr1: memory-controller@8000 { 230 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 231 reg = <0x8000 0x1000>; 232 interrupts = <16 2 1 23>; 233 }; 234 235 ddr2: memory-controller@9000 { 236 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller"; 237 reg = <0x9000 0x1000>; 238 interrupts = <16 2 1 22>; 239 }; 240 241 cpc: l3-cache-controller@10000 { 242 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 243 reg = <0x10000 0x1000 244 0x11000 0x1000>; 245 interrupts = <16 2 1 27 246 16 2 1 26>; 247 }; 248 249 corenet-cf@18000 { 250 compatible = "fsl,corenet-cf"; 251 reg = <0x18000 0x1000>; 252 interrupts = <16 2 1 31>; 253 fsl,ccf-num-csdids = <32>; 254 fsl,ccf-num-snoopids = <32>; 255 }; 256 257 iommu@20000 { 258 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 259 reg = <0x20000 0x4000>; 260 interrupts = < 261 24 2 0 0 262 16 2 1 30>; 263 }; 264 265/include/ "qoriq-mpic.dtsi" 266 267 guts: global-utilities@e0000 { 268 compatible = "fsl,qoriq-device-config-1.0"; 269 reg = <0xe0000 0xe00>; 270 fsl,has-rstcr; 271 #sleep-cells = <1>; 272 fsl,liodn-bits = <12>; 273 }; 274 275 pins: global-utilities@e0e00 { 276 compatible = "fsl,qoriq-pin-control-1.0"; 277 reg = <0xe0e00 0x200>; 278 #sleep-cells = <2>; 279 }; 280 281 clockgen: global-utilities@e1000 { 282 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 283 reg = <0xe1000 0x1000>; 284 clock-frequency = <0>; 285 }; 286 287 rcpm: global-utilities@e2000 { 288 compatible = "fsl,qoriq-rcpm-1.0"; 289 reg = <0xe2000 0x1000>; 290 #sleep-cells = <1>; 291 }; 292 293 sfp: sfp@e8000 { 294 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0"; 295 reg = <0xe8000 0x1000>; 296 }; 297 298 serdes: serdes@ea000 { 299 compatible = "fsl,p5020-serdes"; 300 reg = <0xea000 0x1000>; 301 }; 302 303/include/ "qoriq-dma-0.dtsi" 304/include/ "qoriq-dma-1.dtsi" 305/include/ "qoriq-espi-0.dtsi" 306 spi@110000 { 307 fsl,espi-num-chipselects = <4>; 308 }; 309 310/include/ "qoriq-esdhc-0.dtsi" 311 sdhc@114000 { 312 sdhci,auto-cmd12; 313 }; 314 315/include/ "qoriq-i2c-0.dtsi" 316/include/ "qoriq-i2c-1.dtsi" 317/include/ "qoriq-duart-0.dtsi" 318/include/ "qoriq-duart-1.dtsi" 319/include/ "qoriq-gpio-0.dtsi" 320/include/ "qoriq-usb2-mph-0.dtsi" 321 usb0: usb@210000 { 322 phy_type = "utmi"; 323 port0; 324 }; 325 326/include/ "qoriq-usb2-dr-0.dtsi" 327 usb1: usb@211000 { 328 dr_mode = "host"; 329 phy_type = "utmi"; 330 }; 331 332/include/ "qoriq-sata2-0.dtsi" 333/include/ "qoriq-sata2-1.dtsi" 334/include/ "qoriq-sec4.2-0.dtsi" 335}; 336