1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37	compatible = "fsl,P4080";
38	#address-cells = <2>;
39	#size-cells = <2>;
40	interrupt-parent = <&mpic>;
41
42	aliases {
43		ccsr = &soc;
44		dcsr = &dcsr;
45
46		serial0 = &serial0;
47		serial1 = &serial1;
48		serial2 = &serial2;
49		serial3 = &serial3;
50		pci0 = &pci0;
51		pci1 = &pci1;
52		pci2 = &pci2;
53		usb0 = &usb0;
54		usb1 = &usb1;
55		dma0 = &dma0;
56		dma1 = &dma1;
57		sdhc = &sdhc;
58		msi0 = &msi0;
59		msi1 = &msi1;
60		msi2 = &msi2;
61
62		crypto = &crypto;
63		sec_jr0 = &sec_jr0;
64		sec_jr1 = &sec_jr1;
65		sec_jr2 = &sec_jr2;
66		sec_jr3 = &sec_jr3;
67		rtic_a = &rtic_a;
68		rtic_b = &rtic_b;
69		rtic_c = &rtic_c;
70		rtic_d = &rtic_d;
71		sec_mon = &sec_mon;
72
73		rio0 = &rapidio0;
74	};
75
76	cpus {
77		#address-cells = <1>;
78		#size-cells = <0>;
79
80		cpu0: PowerPC,e500mc@0 {
81			device_type = "cpu";
82			reg = <0>;
83			next-level-cache = <&L2_0>;
84			L2_0: l2-cache {
85				next-level-cache = <&cpc>;
86			};
87		};
88		cpu1: PowerPC,e500mc@1 {
89			device_type = "cpu";
90			reg = <1>;
91			next-level-cache = <&L2_1>;
92			L2_1: l2-cache {
93				next-level-cache = <&cpc>;
94			};
95		};
96		cpu2: PowerPC,e500mc@2 {
97			device_type = "cpu";
98			reg = <2>;
99			next-level-cache = <&L2_2>;
100			L2_2: l2-cache {
101				next-level-cache = <&cpc>;
102			};
103		};
104		cpu3: PowerPC,e500mc@3 {
105			device_type = "cpu";
106			reg = <3>;
107			next-level-cache = <&L2_3>;
108			L2_3: l2-cache {
109				next-level-cache = <&cpc>;
110			};
111		};
112		cpu4: PowerPC,e500mc@4 {
113			device_type = "cpu";
114			reg = <4>;
115			next-level-cache = <&L2_4>;
116			L2_4: l2-cache {
117				next-level-cache = <&cpc>;
118			};
119		};
120		cpu5: PowerPC,e500mc@5 {
121			device_type = "cpu";
122			reg = <5>;
123			next-level-cache = <&L2_5>;
124			L2_5: l2-cache {
125				next-level-cache = <&cpc>;
126			};
127		};
128		cpu6: PowerPC,e500mc@6 {
129			device_type = "cpu";
130			reg = <6>;
131			next-level-cache = <&L2_6>;
132			L2_6: l2-cache {
133				next-level-cache = <&cpc>;
134			};
135		};
136		cpu7: PowerPC,e500mc@7 {
137			device_type = "cpu";
138			reg = <7>;
139			next-level-cache = <&L2_7>;
140			L2_7: l2-cache {
141				next-level-cache = <&cpc>;
142			};
143		};
144	};
145};
146