1/* 2 * P4080/P4040 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 - 2014 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&bman_fbpr { 36 compatible = "fsl,bman-fbpr"; 37 alloc-ranges = <0 0 0x10 0>; 38}; 39 40&lbc { 41 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; 42 interrupts = <25 2 0 0>; 43 #address-cells = <2>; 44 #size-cells = <1>; 45}; 46 47/* controller at 0x200000 */ 48&pci0 { 49 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; 50 device_type = "pci"; 51 #size-cells = <2>; 52 #address-cells = <3>; 53 bus-range = <0x0 0xff>; 54 clock-frequency = <33333333>; 55 interrupts = <16 2 1 15>; 56 fsl,iommu-parent = <&pamu0>; 57 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ 58 pcie@0 { 59 reg = <0 0 0 0 0>; 60 #interrupt-cells = <1>; 61 #size-cells = <2>; 62 #address-cells = <3>; 63 device_type = "pci"; 64 interrupts = <16 2 1 15>; 65 interrupt-map-mask = <0xf800 0 0 7>; 66 interrupt-map = < 67 /* IDSEL 0x0 */ 68 0000 0 0 1 &mpic 40 1 0 0 69 0000 0 0 2 &mpic 1 1 0 0 70 0000 0 0 3 &mpic 2 1 0 0 71 0000 0 0 4 &mpic 3 1 0 0 72 >; 73 }; 74}; 75 76/* controller at 0x201000 */ 77&pci1 { 78 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; 79 device_type = "pci"; 80 #size-cells = <2>; 81 #address-cells = <3>; 82 bus-range = <0 0xff>; 83 clock-frequency = <33333333>; 84 interrupts = <16 2 1 14>; 85 fsl,iommu-parent = <&pamu0>; 86 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ 87 pcie@0 { 88 reg = <0 0 0 0 0>; 89 #interrupt-cells = <1>; 90 #size-cells = <2>; 91 #address-cells = <3>; 92 device_type = "pci"; 93 interrupts = <16 2 1 14>; 94 interrupt-map-mask = <0xf800 0 0 7>; 95 interrupt-map = < 96 /* IDSEL 0x0 */ 97 0000 0 0 1 &mpic 41 1 0 0 98 0000 0 0 2 &mpic 5 1 0 0 99 0000 0 0 3 &mpic 6 1 0 0 100 0000 0 0 4 &mpic 7 1 0 0 101 >; 102 }; 103}; 104 105/* controller at 0x202000 */ 106&pci2 { 107 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; 108 device_type = "pci"; 109 #size-cells = <2>; 110 #address-cells = <3>; 111 bus-range = <0x0 0xff>; 112 clock-frequency = <33333333>; 113 interrupts = <16 2 1 13>; 114 fsl,iommu-parent = <&pamu0>; 115 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ 116 pcie@0 { 117 reg = <0 0 0 0 0>; 118 #interrupt-cells = <1>; 119 #size-cells = <2>; 120 #address-cells = <3>; 121 device_type = "pci"; 122 interrupts = <16 2 1 13>; 123 interrupt-map-mask = <0xf800 0 0 7>; 124 interrupt-map = < 125 /* IDSEL 0x0 */ 126 0000 0 0 1 &mpic 42 1 0 0 127 0000 0 0 2 &mpic 9 1 0 0 128 0000 0 0 3 &mpic 10 1 0 0 129 0000 0 0 4 &mpic 11 1 0 0 130 >; 131 }; 132}; 133 134&rio { 135 compatible = "fsl,srio"; 136 interrupts = <16 2 1 11>; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 fsl,srio-rmu-handle = <&rmu>; 140 fsl,iommu-parent = <&pamu0>; 141 ranges; 142 143 port1 { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 cell-index = <1>; 147 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ 148 }; 149 150 port2 { 151 #address-cells = <2>; 152 #size-cells = <2>; 153 cell-index = <2>; 154 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ 155 }; 156}; 157 158&dcsr { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "fsl,dcsr", "simple-bus"; 162 163 dcsr-epu@0 { 164 compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu"; 165 interrupts = <52 2 0 0 166 84 2 0 0 167 85 2 0 0>; 168 reg = <0x0 0x1000>; 169 }; 170 dcsr-npc { 171 compatible = "fsl,dcsr-npc"; 172 reg = <0x1000 0x1000 0x1000000 0x8000>; 173 }; 174 dcsr-nxc@2000 { 175 compatible = "fsl,dcsr-nxc"; 176 reg = <0x2000 0x1000>; 177 }; 178 dcsr-corenet { 179 compatible = "fsl,dcsr-corenet"; 180 reg = <0x8000 0x1000 0xB0000 0x1000>; 181 }; 182 dcsr-dpaa@9000 { 183 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; 184 reg = <0x9000 0x1000>; 185 }; 186 dcsr-ocn@11000 { 187 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; 188 reg = <0x11000 0x1000>; 189 }; 190 dcsr-ddr@12000 { 191 compatible = "fsl,dcsr-ddr"; 192 dev-handle = <&ddr1>; 193 reg = <0x12000 0x1000>; 194 }; 195 dcsr-ddr@13000 { 196 compatible = "fsl,dcsr-ddr"; 197 dev-handle = <&ddr2>; 198 reg = <0x13000 0x1000>; 199 }; 200 dcsr-nal@18000 { 201 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; 202 reg = <0x18000 0x1000>; 203 }; 204 dcsr-rcpm@22000 { 205 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; 206 reg = <0x22000 0x1000>; 207 }; 208 dcsr-cpu-sb-proxy@40000 { 209 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 210 cpu-handle = <&cpu0>; 211 reg = <0x40000 0x1000>; 212 }; 213 dcsr-cpu-sb-proxy@41000 { 214 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 215 cpu-handle = <&cpu1>; 216 reg = <0x41000 0x1000>; 217 }; 218 dcsr-cpu-sb-proxy@42000 { 219 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 220 cpu-handle = <&cpu2>; 221 reg = <0x42000 0x1000>; 222 }; 223 dcsr-cpu-sb-proxy@43000 { 224 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 225 cpu-handle = <&cpu3>; 226 reg = <0x43000 0x1000>; 227 }; 228 dcsr-cpu-sb-proxy@44000 { 229 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 230 cpu-handle = <&cpu4>; 231 reg = <0x44000 0x1000>; 232 }; 233 dcsr-cpu-sb-proxy@45000 { 234 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 235 cpu-handle = <&cpu5>; 236 reg = <0x45000 0x1000>; 237 }; 238 dcsr-cpu-sb-proxy@46000 { 239 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 240 cpu-handle = <&cpu6>; 241 reg = <0x46000 0x1000>; 242 }; 243 dcsr-cpu-sb-proxy@47000 { 244 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 245 cpu-handle = <&cpu7>; 246 reg = <0x47000 0x1000>; 247 }; 248 249}; 250 251/include/ "qoriq-bman1-portals.dtsi" 252 253&soc { 254 #address-cells = <1>; 255 #size-cells = <1>; 256 device_type = "soc"; 257 compatible = "simple-bus"; 258 259 soc-sram-error { 260 compatible = "fsl,soc-sram-error"; 261 interrupts = <16 2 1 29>; 262 }; 263 264 corenet-law@0 { 265 compatible = "fsl,corenet-law"; 266 reg = <0x0 0x1000>; 267 fsl,num-laws = <32>; 268 }; 269 270 ddr1: memory-controller@8000 { 271 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller"; 272 reg = <0x8000 0x1000>; 273 interrupts = <16 2 1 23>; 274 }; 275 276 ddr2: memory-controller@9000 { 277 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller"; 278 reg = <0x9000 0x1000>; 279 interrupts = <16 2 1 22>; 280 }; 281 282 cpc: l3-cache-controller@10000 { 283 compatible = "fsl,p4080-l3-cache-controller", "cache"; 284 reg = <0x10000 0x1000 285 0x11000 0x1000>; 286 interrupts = <16 2 1 27 287 16 2 1 26>; 288 }; 289 290 corenet-cf@18000 { 291 compatible = "fsl,corenet1-cf", "fsl,corenet-cf"; 292 reg = <0x18000 0x1000>; 293 interrupts = <16 2 1 31>; 294 fsl,ccf-num-csdids = <32>; 295 fsl,ccf-num-snoopids = <32>; 296 }; 297 298 iommu@20000 { 299 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 300 reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */ 301 ranges = <0 0x20000 0x5000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 interrupts = < 305 24 2 0 0 306 16 2 1 30>; 307 fsl,portid-mapping = <0x00f80000>; 308 309 pamu0: pamu@0 { 310 reg = <0 0x1000>; 311 fsl,primary-cache-geometry = <32 1>; 312 fsl,secondary-cache-geometry = <128 2>; 313 }; 314 315 pamu1: pamu@1000 { 316 reg = <0x1000 0x1000>; 317 fsl,primary-cache-geometry = <32 1>; 318 fsl,secondary-cache-geometry = <128 2>; 319 }; 320 321 pamu2: pamu@2000 { 322 reg = <0x2000 0x1000>; 323 fsl,primary-cache-geometry = <32 1>; 324 fsl,secondary-cache-geometry = <128 2>; 325 }; 326 327 pamu3: pamu@3000 { 328 reg = <0x3000 0x1000>; 329 fsl,primary-cache-geometry = <32 1>; 330 fsl,secondary-cache-geometry = <128 2>; 331 }; 332 333 pamu4: pamu@4000 { 334 reg = <0x4000 0x1000>; 335 fsl,primary-cache-geometry = <32 1>; 336 fsl,secondary-cache-geometry = <128 2>; 337 }; 338 }; 339 340/include/ "qoriq-rmu-0.dtsi" 341 rmu@d3000 { 342 fsl,iommu-parent = <&pamu0>; 343 fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */ 344 }; 345 346/include/ "qoriq-mpic.dtsi" 347 348 guts: global-utilities@e0000 { 349 compatible = "fsl,qoriq-device-config-1.0"; 350 reg = <0xe0000 0xe00>; 351 fsl,has-rstcr; 352 #sleep-cells = <1>; 353 fsl,liodn-bits = <12>; 354 }; 355 356 pins: global-utilities@e0e00 { 357 compatible = "fsl,qoriq-pin-control-1.0"; 358 reg = <0xe0e00 0x200>; 359 #sleep-cells = <2>; 360 }; 361 362/include/ "qoriq-clockgen1.dtsi" 363 global-utilities@e1000 { 364 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 365 366 pll2: pll2@840 { 367 #clock-cells = <1>; 368 reg = <0x840 0x4>; 369 compatible = "fsl,qoriq-core-pll-1.0"; 370 clocks = <&sysclk>; 371 clock-output-names = "pll2", "pll2-div2"; 372 }; 373 374 pll3: pll3@860 { 375 #clock-cells = <1>; 376 reg = <0x860 0x4>; 377 compatible = "fsl,qoriq-core-pll-1.0"; 378 clocks = <&sysclk>; 379 clock-output-names = "pll3", "pll3-div2"; 380 }; 381 382 mux2: mux2@40 { 383 #clock-cells = <0>; 384 reg = <0x40 0x4>; 385 compatible = "fsl,qoriq-core-mux-1.0"; 386 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 387 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 388 clock-output-names = "cmux2"; 389 }; 390 391 mux3: mux3@60 { 392 #clock-cells = <0>; 393 reg = <0x60 0x4>; 394 compatible = "fsl,qoriq-core-mux-1.0"; 395 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 396 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 397 clock-output-names = "cmux3"; 398 }; 399 400 mux4: mux4@80 { 401 #clock-cells = <0>; 402 reg = <0x80 0x4>; 403 compatible = "fsl,qoriq-core-mux-1.0"; 404 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 405 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 406 clock-output-names = "cmux4"; 407 }; 408 409 mux5: mux5@a0 { 410 #clock-cells = <0>; 411 reg = <0xa0 0x4>; 412 compatible = "fsl,qoriq-core-mux-1.0"; 413 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 414 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 415 clock-output-names = "cmux5"; 416 }; 417 418 mux6: mux6@c0 { 419 #clock-cells = <0>; 420 reg = <0xc0 0x4>; 421 compatible = "fsl,qoriq-core-mux-1.0"; 422 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 423 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 424 clock-output-names = "cmux6"; 425 }; 426 427 mux7: mux7@e0 { 428 #clock-cells = <0>; 429 reg = <0xe0 0x4>; 430 compatible = "fsl,qoriq-core-mux-1.0"; 431 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 432 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 433 clock-output-names = "cmux7"; 434 }; 435 }; 436 437 rcpm: global-utilities@e2000 { 438 compatible = "fsl,qoriq-rcpm-1.0"; 439 reg = <0xe2000 0x1000>; 440 #sleep-cells = <1>; 441 }; 442 443 sfp: sfp@e8000 { 444 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0"; 445 reg = <0xe8000 0x1000>; 446 }; 447 448 serdes: serdes@ea000 { 449 compatible = "fsl,p4080-serdes"; 450 reg = <0xea000 0x1000>; 451 }; 452 453/include/ "qoriq-dma-0.dtsi" 454 dma@100300 { 455 fsl,iommu-parent = <&pamu0>; 456 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ 457 }; 458 459/include/ "qoriq-dma-1.dtsi" 460 dma@101300 { 461 fsl,iommu-parent = <&pamu0>; 462 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ 463 }; 464 465/include/ "qoriq-espi-0.dtsi" 466 spi@110000 { 467 fsl,espi-num-chipselects = <4>; 468 }; 469 470/include/ "qoriq-esdhc-0.dtsi" 471 sdhc@114000 { 472 compatible = "fsl,p4080-esdhc", "fsl,esdhc"; 473 fsl,iommu-parent = <&pamu1>; 474 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 475 voltage-ranges = <3300 3300>; 476 sdhci,auto-cmd12; 477 }; 478 479/include/ "qoriq-i2c-0.dtsi" 480/include/ "qoriq-i2c-1.dtsi" 481/include/ "qoriq-duart-0.dtsi" 482/include/ "qoriq-duart-1.dtsi" 483/include/ "qoriq-gpio-0.dtsi" 484/include/ "qoriq-usb2-mph-0.dtsi" 485 usb@210000 { 486 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 487 fsl,iommu-parent = <&pamu1>; 488 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 489 port0; 490 }; 491/include/ "qoriq-usb2-dr-0.dtsi" 492 usb@211000 { 493 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 494 fsl,iommu-parent = <&pamu1>; 495 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ 496 }; 497/include/ "qoriq-sec4.0-0.dtsi" 498crypto: crypto@300000 { 499 fsl,iommu-parent = <&pamu1>; 500 }; 501 502/include/ "qoriq-bman1.dtsi" 503}; 504