1/* 2 * P4080/P4040 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; 37 interrupts = <25 2 0 0>; 38 #address-cells = <2>; 39 #size-cells = <1>; 40}; 41 42/* controller at 0x200000 */ 43&pci0 { 44 compatible = "fsl,p4080-pcie"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 clock-frequency = <33333333>; 50 interrupts = <16 2 1 15>; 51 pcie@0 { 52 reg = <0 0 0 0 0>; 53 #interrupt-cells = <1>; 54 #size-cells = <2>; 55 #address-cells = <3>; 56 device_type = "pci"; 57 interrupts = <16 2 1 15>; 58 interrupt-map-mask = <0xf800 0 0 7>; 59 interrupt-map = < 60 /* IDSEL 0x0 */ 61 0000 0 0 1 &mpic 40 1 0 0 62 0000 0 0 2 &mpic 1 1 0 0 63 0000 0 0 3 &mpic 2 1 0 0 64 0000 0 0 4 &mpic 3 1 0 0 65 >; 66 }; 67}; 68 69/* controller at 0x201000 */ 70&pci1 { 71 compatible = "fsl,p4080-pcie"; 72 device_type = "pci"; 73 #size-cells = <2>; 74 #address-cells = <3>; 75 bus-range = <0 0xff>; 76 clock-frequency = <33333333>; 77 interrupts = <16 2 1 14>; 78 pcie@0 { 79 reg = <0 0 0 0 0>; 80 #interrupt-cells = <1>; 81 #size-cells = <2>; 82 #address-cells = <3>; 83 device_type = "pci"; 84 interrupts = <16 2 1 14>; 85 interrupt-map-mask = <0xf800 0 0 7>; 86 interrupt-map = < 87 /* IDSEL 0x0 */ 88 0000 0 0 1 &mpic 41 1 0 0 89 0000 0 0 2 &mpic 5 1 0 0 90 0000 0 0 3 &mpic 6 1 0 0 91 0000 0 0 4 &mpic 7 1 0 0 92 >; 93 }; 94}; 95 96/* controller at 0x202000 */ 97&pci2 { 98 compatible = "fsl,p4080-pcie"; 99 device_type = "pci"; 100 #size-cells = <2>; 101 #address-cells = <3>; 102 bus-range = <0x0 0xff>; 103 clock-frequency = <33333333>; 104 interrupts = <16 2 1 13>; 105 pcie@0 { 106 reg = <0 0 0 0 0>; 107 #interrupt-cells = <1>; 108 #size-cells = <2>; 109 #address-cells = <3>; 110 device_type = "pci"; 111 interrupts = <16 2 1 13>; 112 interrupt-map-mask = <0xf800 0 0 7>; 113 interrupt-map = < 114 /* IDSEL 0x0 */ 115 0000 0 0 1 &mpic 42 1 0 0 116 0000 0 0 2 &mpic 9 1 0 0 117 0000 0 0 3 &mpic 10 1 0 0 118 0000 0 0 4 &mpic 11 1 0 0 119 >; 120 }; 121}; 122 123&rio { 124 #address-cells = <2>; 125 #size-cells = <2>; 126 compatible = "fsl,rapidio-delta"; 127 interrupts = < 128 16 2 1 11 /* err_irq */ 129 56 2 0 0 /* bell_outb_irq */ 130 57 2 0 0 /* bell_inb_irq */ 131 60 2 0 0 /* msg1_tx_irq */ 132 61 2 0 0 /* msg1_rx_irq */ 133 62 2 0 0 /* msg2_tx_irq */ 134 63 2 0 0>; /* msg2_rx_irq */ 135}; 136 137&dcsr { 138 #address-cells = <1>; 139 #size-cells = <1>; 140 compatible = "fsl,dcsr", "simple-bus"; 141 142 dcsr-epu@0 { 143 compatible = "fsl,dcsr-epu"; 144 interrupts = <52 2 0 0 145 84 2 0 0 146 85 2 0 0>; 147 reg = <0x0 0x1000>; 148 }; 149 dcsr-npc { 150 compatible = "fsl,dcsr-npc"; 151 reg = <0x1000 0x1000 0x1000000 0x8000>; 152 }; 153 dcsr-nxc@2000 { 154 compatible = "fsl,dcsr-nxc"; 155 reg = <0x2000 0x1000>; 156 }; 157 dcsr-corenet { 158 compatible = "fsl,dcsr-corenet"; 159 reg = <0x8000 0x1000 0xB0000 0x1000>; 160 }; 161 dcsr-dpaa@9000 { 162 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; 163 reg = <0x9000 0x1000>; 164 }; 165 dcsr-ocn@11000 { 166 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; 167 reg = <0x11000 0x1000>; 168 }; 169 dcsr-ddr@12000 { 170 compatible = "fsl,dcsr-ddr"; 171 dev-handle = <&ddr1>; 172 reg = <0x12000 0x1000>; 173 }; 174 dcsr-ddr@13000 { 175 compatible = "fsl,dcsr-ddr"; 176 dev-handle = <&ddr2>; 177 reg = <0x13000 0x1000>; 178 }; 179 dcsr-nal@18000 { 180 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; 181 reg = <0x18000 0x1000>; 182 }; 183 dcsr-rcpm@22000 { 184 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; 185 reg = <0x22000 0x1000>; 186 }; 187 dcsr-cpu-sb-proxy@40000 { 188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 189 cpu-handle = <&cpu0>; 190 reg = <0x40000 0x1000>; 191 }; 192 dcsr-cpu-sb-proxy@41000 { 193 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 194 cpu-handle = <&cpu1>; 195 reg = <0x41000 0x1000>; 196 }; 197 dcsr-cpu-sb-proxy@42000 { 198 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 199 cpu-handle = <&cpu2>; 200 reg = <0x42000 0x1000>; 201 }; 202 dcsr-cpu-sb-proxy@43000 { 203 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 204 cpu-handle = <&cpu3>; 205 reg = <0x43000 0x1000>; 206 }; 207 dcsr-cpu-sb-proxy@44000 { 208 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 209 cpu-handle = <&cpu4>; 210 reg = <0x44000 0x1000>; 211 }; 212 dcsr-cpu-sb-proxy@45000 { 213 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 214 cpu-handle = <&cpu5>; 215 reg = <0x45000 0x1000>; 216 }; 217 dcsr-cpu-sb-proxy@46000 { 218 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 219 cpu-handle = <&cpu6>; 220 reg = <0x46000 0x1000>; 221 }; 222 dcsr-cpu-sb-proxy@47000 { 223 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 224 cpu-handle = <&cpu7>; 225 reg = <0x47000 0x1000>; 226 }; 227 228}; 229 230&soc { 231 #address-cells = <1>; 232 #size-cells = <1>; 233 device_type = "soc"; 234 compatible = "simple-bus"; 235 236 soc-sram-error { 237 compatible = "fsl,soc-sram-error"; 238 interrupts = <16 2 1 29>; 239 }; 240 241 corenet-law@0 { 242 compatible = "fsl,corenet-law"; 243 reg = <0x0 0x1000>; 244 fsl,num-laws = <32>; 245 }; 246 247 ddr1: memory-controller@8000 { 248 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller"; 249 reg = <0x8000 0x1000>; 250 interrupts = <16 2 1 23>; 251 }; 252 253 ddr2: memory-controller@9000 { 254 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller"; 255 reg = <0x9000 0x1000>; 256 interrupts = <16 2 1 22>; 257 }; 258 259 cpc: l3-cache-controller@10000 { 260 compatible = "fsl,p4080-l3-cache-controller", "cache"; 261 reg = <0x10000 0x1000 262 0x11000 0x1000>; 263 interrupts = <16 2 1 27 264 16 2 1 26>; 265 }; 266 267 corenet-cf@18000 { 268 compatible = "fsl,corenet-cf"; 269 reg = <0x18000 0x1000>; 270 interrupts = <16 2 1 31>; 271 fsl,ccf-num-csdids = <32>; 272 fsl,ccf-num-snoopids = <32>; 273 }; 274 275 iommu@20000 { 276 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 277 reg = <0x20000 0x5000>; 278 interrupts = < 279 24 2 0 0 280 16 2 1 30>; 281 }; 282 283/include/ "qoriq-mpic.dtsi" 284 285 guts: global-utilities@e0000 { 286 compatible = "fsl,qoriq-device-config-1.0"; 287 reg = <0xe0000 0xe00>; 288 fsl,has-rstcr; 289 #sleep-cells = <1>; 290 fsl,liodn-bits = <12>; 291 }; 292 293 pins: global-utilities@e0e00 { 294 compatible = "fsl,qoriq-pin-control-1.0"; 295 reg = <0xe0e00 0x200>; 296 #sleep-cells = <2>; 297 }; 298 299 clockgen: global-utilities@e1000 { 300 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 301 reg = <0xe1000 0x1000>; 302 clock-frequency = <0>; 303 }; 304 305 rcpm: global-utilities@e2000 { 306 compatible = "fsl,qoriq-rcpm-1.0"; 307 reg = <0xe2000 0x1000>; 308 #sleep-cells = <1>; 309 }; 310 311 sfp: sfp@e8000 { 312 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0"; 313 reg = <0xe8000 0x1000>; 314 }; 315 316 serdes: serdes@ea000 { 317 compatible = "fsl,p4080-serdes"; 318 reg = <0xea000 0x1000>; 319 }; 320 321/include/ "qoriq-dma-0.dtsi" 322/include/ "qoriq-dma-1.dtsi" 323/include/ "qoriq-espi-0.dtsi" 324 spi@110000 { 325 fsl,espi-num-chipselects = <4>; 326 }; 327 328/include/ "qoriq-esdhc-0.dtsi" 329 sdhc@114000 { 330 voltage-ranges = <3300 3300>; 331 sdhci,auto-cmd12; 332 }; 333 334/include/ "qoriq-i2c-0.dtsi" 335/include/ "qoriq-i2c-1.dtsi" 336/include/ "qoriq-duart-0.dtsi" 337/include/ "qoriq-duart-1.dtsi" 338/include/ "qoriq-gpio-0.dtsi" 339/include/ "qoriq-usb2-mph-0.dtsi" 340/include/ "qoriq-usb2-dr-0.dtsi" 341/include/ "qoriq-sec4.0-0.dtsi" 342}; 343