1/* 2 * P4080DS Device Tree Source 3 * 4 * Copyright 2009 - 2014 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p4080si-pre.dtsi" 36 37/ { 38 model = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 memory { 45 device_type = "memory"; 46 }; 47 48 reserved-memory { 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges; 52 53 bman_fbpr: bman-fbpr { 54 size = <0 0x1000000>; 55 alignment = <0 0x1000000>; 56 }; 57 qman_fqd: qman-fqd { 58 size = <0 0x400000>; 59 alignment = <0 0x400000>; 60 }; 61 qman_pfdr: qman-pfdr { 62 size = <0 0x2000000>; 63 alignment = <0 0x2000000>; 64 }; 65 }; 66 67 dcsr: dcsr@f00000000 { 68 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 69 }; 70 71 bportals: bman-portals@ff4000000 { 72 ranges = <0x0 0xf 0xf4000000 0x200000>; 73 }; 74 75 qportals: qman-portals@ff4200000 { 76 ranges = <0x0 0xf 0xf4200000 0x200000>; 77 }; 78 79 soc: soc@ffe000000 { 80 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 81 reg = <0xf 0xfe000000 0 0x00001000>; 82 83 spi@110000 { 84 flash@0 { 85 #address-cells = <1>; 86 #size-cells = <1>; 87 compatible = "spansion,s25sl12801"; 88 reg = <0>; 89 spi-max-frequency = <40000000>; /* input clock */ 90 partition@u-boot { 91 label = "u-boot"; 92 reg = <0x00000000 0x00100000>; 93 read-only; 94 }; 95 partition@kernel { 96 label = "kernel"; 97 reg = <0x00100000 0x00500000>; 98 read-only; 99 }; 100 partition@dtb { 101 label = "dtb"; 102 reg = <0x00600000 0x00100000>; 103 read-only; 104 }; 105 partition@fs { 106 label = "file system"; 107 reg = <0x00700000 0x00900000>; 108 }; 109 }; 110 }; 111 112 i2c@118100 { 113 eeprom@51 { 114 compatible = "at24,24c256"; 115 reg = <0x51>; 116 }; 117 eeprom@52 { 118 compatible = "at24,24c256"; 119 reg = <0x52>; 120 }; 121 rtc@68 { 122 compatible = "dallas,ds3232"; 123 reg = <0x68>; 124 interrupts = <0x1 0x1 0 0>; 125 }; 126 adt7461@4c { 127 compatible = "adi,adt7461"; 128 reg = <0x4c>; 129 }; 130 }; 131 132 usb0: usb@210000 { 133 phy_type = "ulpi"; 134 }; 135 136 usb1: usb@211000 { 137 dr_mode = "host"; 138 phy_type = "ulpi"; 139 }; 140 }; 141 142 rio: rapidio@ffe0c0000 { 143 reg = <0xf 0xfe0c0000 0 0x11000>; 144 145 port1 { 146 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 147 }; 148 port2 { 149 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 150 }; 151 }; 152 153 lbc: localbus@ffe124000 { 154 reg = <0xf 0xfe124000 0 0x1000>; 155 ranges = <0 0 0xf 0xe8000000 0x08000000 156 3 0 0xf 0xffdf0000 0x00008000>; 157 158 flash@0,0 { 159 compatible = "cfi-flash"; 160 reg = <0 0 0x08000000>; 161 bank-width = <2>; 162 device-width = <2>; 163 }; 164 165 board-control@3,0 { 166 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; 167 reg = <3 0 0x30>; 168 }; 169 }; 170 171 pci0: pcie@ffe200000 { 172 reg = <0xf 0xfe200000 0 0x1000>; 173 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 174 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 175 pcie@0 { 176 ranges = <0x02000000 0 0xe0000000 177 0x02000000 0 0xe0000000 178 0 0x20000000 179 180 0x01000000 0 0x00000000 181 0x01000000 0 0x00000000 182 0 0x00010000>; 183 }; 184 }; 185 186 pci1: pcie@ffe201000 { 187 reg = <0xf 0xfe201000 0 0x1000>; 188 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 189 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 190 pcie@0 { 191 ranges = <0x02000000 0 0xe0000000 192 0x02000000 0 0xe0000000 193 0 0x20000000 194 195 0x01000000 0 0x00000000 196 0x01000000 0 0x00000000 197 0 0x00010000>; 198 }; 199 }; 200 201 pci2: pcie@ffe202000 { 202 reg = <0xf 0xfe202000 0 0x1000>; 203 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 204 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 205 pcie@0 { 206 ranges = <0x02000000 0 0xe0000000 207 0x02000000 0 0xe0000000 208 0 0x20000000 209 210 0x01000000 0 0x00000000 211 0x01000000 0 0x00000000 212 0 0x00010000>; 213 }; 214 }; 215 216}; 217 218/include/ "p4080si-post.dtsi" 219