xref: /openbmc/linux/scripts/dtc/include-prefixes/powerpc/fsl/p1010rdb_36b.dtsi (revision dc37374b)

/*
 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
 *
 * Copyright 2013 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

memory {
	device_type = "memory";
};

board_ifc: ifc: ifc@fffe1e000 {
	/* NOR, NAND Flashes and CPLD on board */
	ranges = <0x0 0x0 0xf 0xee000000 0x02000000
		  0x1 0x0 0xf 0xff800000 0x00010000
		  0x3 0x0 0xf 0xffb00000 0x00000020>;
	reg = <0xf 0xffe1e000 0 0x2000>;
};

board_soc: soc: soc@fffe00000 {
	ranges = <0x0 0xf 0xffe00000 0x100000>;
};

pci0: pcie@fffe09000 {
	reg = <0xf 0xffe09000 0 0x1000>;
	ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
		  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
	pcie@0 {
		ranges = <0x2000000 0x0 0xc0000000
			  0x2000000 0x0 0xc0000000
			  0x0 0x20000000

			  0x1000000 0x0 0x0
			  0x1000000 0x0 0x0
			  0x0 0x100000>;
	};
};

pci1: pcie@fffe0a000 {
	reg = <0xf 0xffe0a000 0 0x1000>;
	ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
		  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
	pcie@0 {
		ranges = <0x2000000 0x0 0xc0000000
			  0x2000000 0x0 0xc0000000
			  0x0 0x20000000

			  0x1000000 0x0 0x0
			  0x1000000 0x0 0x0
			  0x0 0x100000>;
	};
};