1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35memory {
36	device_type = "memory";
37};
38
39board_ifc: ifc: ifc@ffe1e000 {
40	/* NOR, NAND Flashes and CPLD on board */
41	ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42		  0x1 0x0 0x0 0xff800000 0x00010000
43		  0x3 0x0 0x0 0xffb00000 0x00000020>;
44	reg = <0x0 0xffe1e000 0 0x2000>;
45};
46
47board_soc: soc: soc@ffe00000 {
48	ranges = <0x0 0x0 0xffe00000 0x100000>;
49};
50
51pci0: pcie@ffe09000 {
52	reg = <0 0xffe09000 0 0x1000>;
53	ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54		  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55	pcie@0 {
56		ranges = <0x2000000 0x0 0xa0000000
57			  0x2000000 0x0 0xa0000000
58			  0x0 0x20000000
59
60			  0x1000000 0x0 0x0
61			  0x1000000 0x0 0x0
62			  0x0 0x100000>;
63	};
64};
65
66pci1: pcie@ffe0a000 {
67	reg = <0 0xffe0a000 0 0x1000>;
68	ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
69		  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
70	pcie@0 {
71		ranges = <0x2000000 0x0 0x80000000
72			  0x2000000 0x0 0x80000000
73			  0x0 0x20000000
74
75			  0x1000000 0x0 0x0
76			  0x1000000 0x0 0x0
77			  0x0 0x100000>;
78	};
79};
80