1/*
2 * MPC8569 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36	#address-cells = <2>;
37	#size-cells = <1>;
38	compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
39	interrupts = <19 2 0 0>;
40	sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0xa000 */
44&pci1 {
45	compatible = "fsl,mpc8548-pcie";
46	device_type = "pci";
47	#size-cells = <2>;
48	#address-cells = <3>;
49	bus-range = <0 255>;
50	clock-frequency = <33333333>;
51	interrupts = <26 2 0 0>;
52	sleep = <&pmc 0x20000000>;
53
54	pcie@0 {
55		reg = <0 0 0 0 0>;
56		#interrupt-cells = <1>;
57		#size-cells = <2>;
58		#address-cells = <3>;
59		device_type = "pci";
60		interrupts = <26 2 0 0>;
61		interrupt-map-mask = <0xf800 0 0 7>;
62		interrupt-map = <
63			/* IDSEL 0x0 */
64			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
65			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
66			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
67			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
68			>;
69	};
70};
71
72&rio {
73	#address-cells = <2>;
74	#size-cells = <2>;
75	compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
76	interrupts = <48 2 0 0 /* error     */
77		      49 2 0 0 /* bell_outb */
78		      50 2 0 0 /* bell_inb  */
79		      53 2 0 0 /* msg1_tx   */
80		      54 2 0 0 /* msg1_rx   */
81		      55 2 0 0 /* msg2_tx   */
82		      56 2 0 0 /* msg2_rx   */>;
83	sleep = <&pmc 0x00080000>;
84};
85
86&soc {
87	#address-cells = <1>;
88	#size-cells = <1>;
89	device_type = "soc";
90	compatible = "fsl,mpc8569-immr", "simple-bus";
91	bus-frequency = <0>;		// Filled out by uboot.
92
93	ecm-law@0 {
94		compatible = "fsl,ecm-law";
95		reg = <0x0 0x1000>;
96		fsl,num-laws = <10>;
97	};
98
99	ecm@1000 {
100		compatible = "fsl,mpc8569-ecm", "fsl,ecm";
101		reg = <0x1000 0x1000>;
102		interrupts = <17 2 0 0>;
103	};
104
105	memory-controller@2000 {
106		compatible = "fsl,mpc8569-memory-controller";
107		reg = <0x2000 0x1000>;
108		interrupts = <18 2 0 0>;
109	};
110
111	i2c-sleep-nexus {
112		#address-cells = <1>;
113		#size-cells = <1>;
114		compatible = "simple-bus";
115		sleep = <&pmc 0x00000004>;
116		ranges;
117
118/include/ "pq3-i2c-0.dtsi"
119/include/ "pq3-i2c-1.dtsi"
120
121	};
122
123	duart-sleep-nexus {
124		#address-cells = <1>;
125		#size-cells = <1>;
126		compatible = "simple-bus";
127		sleep = <&pmc 0x00000002>;
128		ranges;
129
130/include/ "pq3-duart-0.dtsi"
131
132	};
133
134	L2: l2-cache-controller@20000 {
135		compatible = "fsl,mpc8569-l2-cache-controller";
136		reg = <0x20000 0x1000>;
137		cache-line-size = <32>;	// 32 bytes
138		cache-size = <0x80000>; // L2, 512K
139		interrupts = <16 2 0 0>;
140	};
141
142/include/ "pq3-dma-0.dtsi"
143/include/ "pq3-esdhc-0.dtsi"
144	sdhc@2e000 {
145		sleep = <&pmc 0x00200000>;
146	};
147
148	par_io@e0100 {
149		#address-cells = <1>;
150		#size-cells = <1>;
151		reg = <0xe0100 0x100>;
152		ranges = <0x0 0xe0100 0x100>;
153		device_type = "par_io";
154	};
155
156/include/ "pq3-sec3.1-0.dtsi"
157	crypto@30000 {
158		sleep = <&pmc 0x01000000>;
159	};
160
161/include/ "pq3-mpic.dtsi"
162
163	global-utilities@e0000 {
164		#address-cells = <1>;
165		#size-cells = <1>;
166		compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
167		reg = <0xe0000 0x1000>;
168		ranges = <0 0xe0000 0x1000>;
169		fsl,has-rstcr;
170
171		pmc: power@70 {
172			compatible = "fsl,mpc8569-pmc",
173				     "fsl,mpc8548-pmc";
174			reg = <0x70 0x20>;
175		};
176	};
177};
178
179&qe {
180	#address-cells = <1>;
181	#size-cells = <1>;
182	device_type = "qe";
183	compatible = "fsl,qe";
184	sleep = <&pmc 0x00000800>;
185	brg-frequency = <0>;
186	bus-frequency = <0>;
187	fsl,qe-num-riscs = <4>;
188	fsl,qe-num-snums = <46>;
189
190	qeic: interrupt-controller@80 {
191		interrupt-controller;
192		compatible = "fsl,qe-ic";
193		#address-cells = <0>;
194		#interrupt-cells = <1>;
195		reg = <0x80 0x80>;
196		interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
197		interrupt-parent = <&mpic>;
198	};
199
200	timer@440 {
201		compatible = "fsl,mpc8569-qe-gtm",
202			     "fsl,qe-gtm", "fsl,gtm";
203		reg = <0x440 0x40>;
204		interrupts = <12 13 14 15>;
205		interrupt-parent = <&qeic>;
206		/* Filled in by U-Boot */
207		clock-frequency = <0>;
208	};
209
210	spi@4c0 {
211		#address-cells = <1>;
212		#size-cells = <0>;
213		compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
214		reg = <0x4c0 0x40>;
215		cell-index = <0>;
216		interrupts = <2>;
217		interrupt-parent = <&qeic>;
218	};
219
220	spi@500 {
221		#address-cells = <1>;
222		#size-cells = <0>;
223		cell-index = <1>;
224		compatible = "fsl,spi";
225		reg = <0x500 0x40>;
226		interrupts = <1>;
227		interrupt-parent = <&qeic>;
228	};
229
230	usb@6c0 {
231		compatible = "fsl,mpc8569-qe-usb",
232			     "fsl,mpc8323-qe-usb";
233		reg = <0x6c0 0x40 0x8b00 0x100>;
234		interrupts = <11>;
235		interrupt-parent = <&qeic>;
236	};
237
238	ucc@2000 {
239		cell-index = <1>;
240		reg = <0x2000 0x200>;
241		interrupts = <32>;
242		interrupt-parent = <&qeic>;
243	};
244
245	ucc@2200 {
246		cell-index = <3>;
247		reg = <0x2200 0x200>;
248		interrupts = <34>;
249		interrupt-parent = <&qeic>;
250	};
251
252	ucc@3000 {
253		cell-index = <2>;
254		reg = <0x3000 0x200>;
255		interrupts = <33>;
256		interrupt-parent = <&qeic>;
257	};
258
259	ucc@3200 {
260		cell-index = <4>;
261		reg = <0x3200 0x200>;
262		interrupts = <35>;
263		interrupt-parent = <&qeic>;
264	};
265
266	ucc@3400 {
267		cell-index = <6>;
268		reg = <0x3400 0x200>;
269		interrupts = <41>;
270		interrupt-parent = <&qeic>;
271	};
272
273	ucc@3600 {
274		cell-index = <8>;
275		reg = <0x3600 0x200>;
276		interrupts = <43>;
277		interrupt-parent = <&qeic>;
278	};
279
280	muram@10000 {
281		#address-cells = <1>;
282		#size-cells = <1>;
283		compatible = "fsl,qe-muram", "fsl,cpm-muram";
284		ranges = <0x0 0x10000 0x20000>;
285
286		data-only@0 {
287			compatible = "fsl,qe-muram-data",
288				     "fsl,cpm-muram-data";
289			reg = <0x0 0x20000>;
290		};
291	};
292};
293