1/*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/include/ "mpc8568si-pre.dtsi"
13
14/ {
15	model = "MPC8568EMDS";
16	compatible = "MPC8568EMDS", "MPC85xxMDS";
17
18	aliases {
19		pci0 = &pci0;
20		pci1 = &pci1;
21		rapidio0 = &rio;
22	};
23
24	memory {
25		device_type = "memory";
26		reg = <0x0 0x0 0x0 0x0>;
27	};
28
29	lbc: localbus@e0005000 {
30		reg = <0x0 0xe0005000 0x0 0x1000>;
31		ranges = <0x0 0x0 0xfe000000 0x02000000
32			  0x1 0x0 0xf8000000 0x00008000
33			  0x2 0x0 0xf0000000 0x04000000
34			  0x4 0x0 0xf8008000 0x00008000
35			  0x5 0x0 0xf8010000 0x00008000>;
36
37		nor@0,0 {
38			#address-cells = <1>;
39			#size-cells = <1>;
40			compatible = "cfi-flash";
41			reg = <0x0 0x0 0x02000000>;
42			bank-width = <2>;
43			device-width = <2>;
44		};
45
46		bcsr@1,0 {
47			#address-cells = <1>;
48			#size-cells = <1>;
49			compatible = "fsl,mpc8568mds-bcsr";
50			reg = <1 0 0x8000>;
51			ranges = <0 1 0 0x8000>;
52
53			bcsr5: gpio-controller@11 {
54				#gpio-cells = <2>;
55				compatible = "fsl,mpc8568mds-bcsr-gpio";
56				reg = <0x5 0x1>;
57				gpio-controller;
58			};
59		};
60
61		pib@4,0 {
62			compatible = "fsl,mpc8568mds-pib";
63			reg = <4 0 0x8000>;
64		};
65
66		pib@5,0 {
67			compatible = "fsl,mpc8568mds-pib";
68			reg = <5 0 0x8000>;
69		};
70	};
71
72	soc: soc8568@e0000000 {
73		ranges = <0x0 0x0 0xe0000000 0x100000>;
74
75		i2c-sleep-nexus {
76			i2c@3000 {
77				rtc@68 {
78					compatible = "dallas,ds1374";
79					reg = <0x68>;
80					interrupts = <3 1 0 0>;
81				};
82			};
83		};
84
85		enet0: ethernet@24000 {
86			tbi-handle = <&tbi0>;
87			phy-handle = <&phy2>;
88		};
89
90		mdio@24520 {
91			phy0: ethernet-phy@7 {
92				interrupts = <1 1 0 0>;
93				reg = <0x7>;
94			};
95			phy1: ethernet-phy@1 {
96				interrupts = <2 1 0 0>;
97				reg = <0x1>;
98			};
99			phy2: ethernet-phy@2 {
100				interrupts = <1 1 0 0>;
101				reg = <0x2>;
102			};
103			phy3: ethernet-phy@3 {
104				interrupts = <2 1 0 0>;
105				reg = <0x3>;
106			};
107			tbi0: tbi-phy@11 {
108				reg = <0x11>;
109				device_type = "tbi-phy";
110			};
111		};
112
113		enet1: ethernet@25000 {
114			tbi-handle = <&tbi1>;
115			phy-handle = <&phy3>;
116			sleep = <&pmc 0x00000040>;
117		};
118
119		mdio@25520 {
120			tbi1: tbi-phy@11 {
121				reg = <0x11>;
122				device_type = "tbi-phy";
123			};
124		};
125
126		par_io@e0100 {
127			num-ports = <7>;
128
129			pio1: ucc_pin@1 {
130				pio-map = <
131			/* port  pin  dir  open_drain  assignment  has_irq */
132					0x4  0xa  0x1  0x0  0x2  0x0 	/* TxD0 */
133					0x4  0x9  0x1  0x0  0x2  0x0 	/* TxD1 */
134					0x4  0x8  0x1  0x0  0x2  0x0 	/* TxD2 */
135					0x4  0x7  0x1  0x0  0x2  0x0 	/* TxD3 */
136					0x4  0x17  0x1  0x0  0x2  0x0 	/* TxD4 */
137					0x4  0x16  0x1  0x0  0x2  0x0 	/* TxD5 */
138					0x4  0x15  0x1  0x0  0x2  0x0 	/* TxD6 */
139					0x4  0x14  0x1  0x0  0x2  0x0 	/* TxD7 */
140					0x4  0xf  0x2  0x0  0x2  0x0 	/* RxD0 */
141					0x4  0xe  0x2  0x0  0x2  0x0 	/* RxD1 */
142					0x4  0xd  0x2  0x0  0x2  0x0 	/* RxD2 */
143					0x4  0xc  0x2  0x0  0x2  0x0 	/* RxD3 */
144					0x4  0x1d  0x2  0x0  0x2  0x0 	/* RxD4 */
145					0x4  0x1c  0x2  0x0  0x2  0x0 	/* RxD5 */
146					0x4  0x1b  0x2  0x0  0x2  0x0 	/* RxD6 */
147					0x4  0x1a  0x2  0x0  0x2  0x0 	/* RxD7 */
148					0x4  0xb  0x1  0x0  0x2  0x0 	/* TX_EN */
149					0x4  0x18  0x1  0x0  0x2  0x0 	/* TX_ER */
150					0x4  0x10  0x2  0x0  0x2  0x0 	/* RX_DV */
151					0x4  0x1e  0x2  0x0  0x2  0x0 	/* RX_ER */
152					0x4  0x11  0x2  0x0  0x2  0x0 	/* RX_CLK */
153					0x4  0x13  0x1  0x0  0x2  0x0 	/* GTX_CLK */
154					0x1  0x1f  0x2  0x0  0x3  0x0>;	/* GTX125 */
155			};
156
157			pio2: ucc_pin@2 {
158				pio-map = <
159			/* port  pin  dir  open_drain  assignment  has_irq */
160					0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
161					0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
162					0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
163					0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
164					0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
165					0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
166					0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
167					0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
168					0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
169					0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
170					0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
171					0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
172					0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
173					0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
174					0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
175					0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
176					0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
177					0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
178					0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
179					0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
180					0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
181					0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
182					0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
183					0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
184					0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
185			};
186		};
187	};
188
189	qe: qe@e0080000 {
190		ranges = <0x0 0x0 0xe0080000 0x40000>;
191		reg = <0x0 0xe0080000 0x0 0x480>;
192
193		spi@4c0 {
194			mode = "cpu";
195		};
196
197		spi@500 {
198			mode = "cpu";
199		};
200
201		enet2: ucc@2000 {
202			device_type = "network";
203			compatible = "ucc_geth";
204			local-mac-address = [ 00 00 00 00 00 00 ];
205			rx-clock-name = "none";
206			tx-clock-name = "clk16";
207			pio-handle = <&pio1>;
208			phy-handle = <&phy0>;
209			phy-connection-type = "rgmii-id";
210		};
211
212		enet3: ucc@3000 {
213			device_type = "network";
214			compatible = "ucc_geth";
215			local-mac-address = [ 00 00 00 00 00 00 ];
216			rx-clock-name = "none";
217			tx-clock-name = "clk16";
218			pio-handle = <&pio2>;
219			phy-handle = <&phy1>;
220			phy-connection-type = "rgmii-id";
221		};
222
223		mdio@2120 {
224			#address-cells = <1>;
225			#size-cells = <0>;
226			reg = <0x2120 0x18>;
227			compatible = "fsl,ucc-mdio";
228
229			/* These are the same PHYs as on
230			 * gianfar's MDIO bus */
231			qe_phy0: ethernet-phy@7 {
232				interrupt-parent = <&mpic>;
233				interrupts = <1 1 0 0>;
234				reg = <0x7>;
235			};
236			qe_phy1: ethernet-phy@1 {
237				interrupt-parent = <&mpic>;
238				interrupts = <2 1 0 0>;
239				reg = <0x1>;
240			};
241			qe_phy2: ethernet-phy@2 {
242				interrupt-parent = <&mpic>;
243				interrupts = <1 1 0 0>;
244				reg = <0x2>;
245			};
246			qe_phy3: ethernet-phy@3 {
247				interrupt-parent = <&mpic>;
248				interrupts = <2 1 0 0>;
249				reg = <0x3>;
250			};
251		};
252	};
253
254	pci0: pci@e0008000 {
255		reg = <0x0 0xe0008000 0x0 0x1000>;
256		ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
257			  0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
258		clock-frequency = <66666666>;
259		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
260		interrupt-map = <
261			/* IDSEL 0x12 AD18 */
262			0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
263			0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
264			0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
265			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
266
267			/* IDSEL 0x13 AD19 */
268			0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
269			0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
270			0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
271			0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
272	};
273
274	/* PCI Express */
275	pci1: pcie@e000a000 {
276		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
277			  0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
278		reg = <0x0 0xe000a000 0x0 0x1000>;
279		pcie@0 {
280			ranges = <0x2000000 0x0 0xa0000000
281				  0x2000000 0x0 0xa0000000
282				  0x0 0x10000000
283
284				  0x1000000 0x0 0x0
285				  0x1000000 0x0 0x0
286				  0x0 0x800000>;
287		};
288	};
289
290	rio: rapidio@e00c00000 {
291		reg = <0x0 0xe00c0000 0x0 0x20000>;
292		port1 {
293			ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
294		};
295	};
296
297	leds {
298		compatible = "gpio-leds";
299
300		green {
301			gpios = <&bcsr5 1 0>;
302		};
303
304		amber {
305			gpios = <&bcsr5 2 0>;
306		};
307
308		red {
309			gpios = <&bcsr5 3 0>;
310		};
311	};
312};
313
314/include/ "mpc8568si-post.dtsi"
315