1/*
2 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
3 *
4 * (C) Copyright 2014
5 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
6 *
7 * Copyright 2011 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 */
14
15/include/ "p2041si-pre.dtsi"
16
17/ {
18	model = "keymile,kmcoge4";
19	compatible = "keymile,kmcoge4", "keymile,kmp204x";
20	#address-cells = <2>;
21	#size-cells = <2>;
22	interrupt-parent = <&mpic>;
23
24	memory {
25		device_type = "memory";
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		bman_fbpr: bman-fbpr {
34			size = <0 0x1000000>;
35			alignment = <0 0x1000000>;
36		};
37		qman_fqd: qman-fqd {
38			size = <0 0x400000>;
39			alignment = <0 0x400000>;
40		};
41		qman_pfdr: qman-pfdr {
42			size = <0 0x2000000>;
43			alignment = <0 0x2000000>;
44		};
45	};
46
47	dcsr: dcsr@f00000000 {
48		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
49	};
50
51	bportals: bman-portals@ff4000000 {
52		ranges = <0x0 0xf 0xf4000000 0x200000>;
53	};
54
55	qportals: qman-portals@ff4200000 {
56		ranges = <0x0 0xf 0xf4200000 0x200000>;
57	};
58
59	soc: soc@ffe000000 {
60		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
61		reg = <0xf 0xfe000000 0 0x00001000>;
62		spi@110000 {
63			flash@0 {
64				#address-cells = <1>;
65				#size-cells = <1>;
66				compatible = "spansion,s25fl256s1", "jedec,spi-nor";
67				reg = <0>;
68				spi-max-frequency = <20000000>; /* input clock */
69			};
70
71			network_clock@1 {
72				compatible = "zarlink,zl30343";
73				reg = <1>;
74				spi-max-frequency = <8000000>;
75			};
76
77			flash@2 {
78				#address-cells = <1>;
79				#size-cells = <1>;
80				compatible = "micron,m25p32", "jedec,spi-nor";
81				reg = <2>;
82				spi-max-frequency = <15000000>;
83			};
84		};
85
86		sdhc@114000 {
87			status = "disabled";
88		};
89
90		i2c@119000 {
91			status = "disabled";
92		};
93
94		i2c@119100 {
95			status = "disabled";
96		};
97
98		usb0: usb@210000 {
99			status = "disabled";
100		};
101
102		usb1: usb@211000 {
103			status = "disabled";
104		};
105
106		sata@220000 {
107			status = "disabled";
108		};
109
110		sata@221000 {
111			status = "disabled";
112		};
113
114		fman0: fman@400000 {
115			enet0: ethernet@e0000 {
116				phy-connection-type = "sgmii";
117				fixed-link {
118					speed = <1000>;
119					full-duplex;
120				};
121			};
122			mdio0: mdio@e1120 {
123				front_phy: ethernet-phy@11 {
124					reg = <0x11>;
125				};
126			};
127
128			enet1: ethernet@e2000 {
129				phy-connection-type = "sgmii";
130				fixed-link {
131					speed = <1000>;
132					full-duplex;
133				};
134			};
135			enet2: ethernet@e4000 {
136				status = "disabled";
137			};
138
139			enet3: ethernet@e6000 {
140				status = "disabled";
141			};
142			enet4: ethernet@e8000 {
143				phy-handle = <&front_phy>;
144				phy-connection-type = "rgmii";
145			};
146			enet5: ethernet@f0000 {
147				status = "disabled";
148			};
149		};
150	};
151
152	rio: rapidio@ffe0c0000 {
153		status = "disabled";
154	};
155
156	lbc: localbus@ffe124000 {
157		reg = <0xf 0xfe124000 0 0x1000>;
158		ranges = <0 0 0xf 0xffa00000 0x00040000		/* LB 0 */
159			  1 0 0xf 0xfb000000 0x00010000		/* LB 1 */
160			  2 0 0xf 0xd0000000 0x10000000		/* LB 2 */
161			  3 0 0xf 0xe0000000 0x10000000>;	/* LB 3 */
162
163		nand@0,0 {
164			#address-cells = <1>;
165			#size-cells = <1>;
166			compatible = "fsl,elbc-fcm-nand";
167			reg = <0 0 0x40000>;
168		};
169
170		board-control@1,0 {
171			compatible = "keymile,qriox";
172			reg = <1 0 0x80>;
173		};
174
175		chassis-mgmt@3,0 {
176			compatible = "keymile,bfticu";
177			interrupt-controller;
178			#interrupt-cells = <2>;
179			reg = <3 0 0x100>;
180			interrupt-parent = <&mpic>;
181			interrupts = <6 1 0 0>;
182		};
183	};
184
185	pci0: pcie@ffe200000 {
186		reg = <0xf 0xfe200000 0 0x1000>;
187		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
188			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
189		pcie@0 {
190			ranges = <0x02000000 0 0xe0000000
191				  0x02000000 0 0xe0000000
192				  0 0x20000000
193
194				  0x01000000 0 0x00000000
195				  0x01000000 0 0x00000000
196				  0 0x00010000>;
197		};
198	};
199
200	pci1: pcie@ffe201000 {
201		status = "disabled";
202	};
203
204	pci2: pcie@ffe202000 {
205		reg = <0xf 0xfe202000 0 0x1000>;
206		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
207			  0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
208		pcie@0 {
209			ranges = <0x02000000 0 0xe0000000
210				  0x02000000 0 0xe0000000
211				  0 0x20000000
212
213				  0x01000000 0 0x00000000
214				  0x01000000 0 0x00000000
215				  0 0x00010000>;
216		};
217	};
218};
219
220/include/ "p2041si-post.dtsi"
221