12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later
2fdc8c4adSValentin Longchamp/*
3fdc8c4adSValentin Longchamp * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
4fdc8c4adSValentin Longchamp *
5fdc8c4adSValentin Longchamp * (C) Copyright 2016
6fdc8c4adSValentin Longchamp * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
7fdc8c4adSValentin Longchamp *
8fdc8c4adSValentin Longchamp * Copyright 2014 - 2015 Freescale Semiconductor Inc.
9fdc8c4adSValentin Longchamp */
10fdc8c4adSValentin Longchamp
11fdc8c4adSValentin Longchamp/include/ "t104xsi-pre.dtsi"
12fdc8c4adSValentin Longchamp
13fdc8c4adSValentin Longchamp/ {
14fdc8c4adSValentin Longchamp	model = "keymile,kmcent2";
15fdc8c4adSValentin Longchamp	compatible = "keymile,kmcent2";
16fdc8c4adSValentin Longchamp
17fdc8c4adSValentin Longchamp	aliases {
18fdc8c4adSValentin Longchamp		front_phy = &front_phy;
19fdc8c4adSValentin Longchamp	};
20fdc8c4adSValentin Longchamp
21fdc8c4adSValentin Longchamp	reserved-memory {
22fdc8c4adSValentin Longchamp		#address-cells = <2>;
23fdc8c4adSValentin Longchamp		#size-cells = <2>;
24fdc8c4adSValentin Longchamp		ranges;
25fdc8c4adSValentin Longchamp
26fdc8c4adSValentin Longchamp		bman_fbpr: bman-fbpr {
27fdc8c4adSValentin Longchamp			size = <0 0x1000000>;
28fdc8c4adSValentin Longchamp			alignment = <0 0x1000000>;
29fdc8c4adSValentin Longchamp		};
30fdc8c4adSValentin Longchamp		qman_fqd: qman-fqd {
31fdc8c4adSValentin Longchamp			size = <0 0x400000>;
32fdc8c4adSValentin Longchamp			alignment = <0 0x400000>;
33fdc8c4adSValentin Longchamp		};
34fdc8c4adSValentin Longchamp		qman_pfdr: qman-pfdr {
35fdc8c4adSValentin Longchamp			size = <0 0x2000000>;
36fdc8c4adSValentin Longchamp			alignment = <0 0x2000000>;
37fdc8c4adSValentin Longchamp		};
38fdc8c4adSValentin Longchamp	};
39fdc8c4adSValentin Longchamp
40fdc8c4adSValentin Longchamp	ifc: localbus@ffe124000 {
41fdc8c4adSValentin Longchamp		reg = <0xf 0xfe124000 0 0x2000>;
42fdc8c4adSValentin Longchamp		ranges = <0 0 0xf 0xe8000000 0x04000000
43fdc8c4adSValentin Longchamp			  1 0 0xf 0xfa000000 0x00010000
44fdc8c4adSValentin Longchamp			  2 0 0xf 0xfb000000 0x00010000
45fdc8c4adSValentin Longchamp			  4 0 0xf 0xc0000000 0x08000000
46fdc8c4adSValentin Longchamp			  6 0 0xf 0xd0000000 0x08000000
47fdc8c4adSValentin Longchamp			  7 0 0xf 0xd8000000 0x08000000>;
48fdc8c4adSValentin Longchamp
49fdc8c4adSValentin Longchamp		nor@0,0 {
50fdc8c4adSValentin Longchamp			#address-cells = <1>;
51fdc8c4adSValentin Longchamp			#size-cells = <1>;
52fdc8c4adSValentin Longchamp			compatible = "cfi-flash";
53fdc8c4adSValentin Longchamp			reg = <0x0 0x0 0x04000000>;
54fdc8c4adSValentin Longchamp			bank-width = <2>;
55fdc8c4adSValentin Longchamp			device-width = <2>;
56fdc8c4adSValentin Longchamp		};
57fdc8c4adSValentin Longchamp
58fdc8c4adSValentin Longchamp		nand@1,0 {
59fdc8c4adSValentin Longchamp			#address-cells = <1>;
60fdc8c4adSValentin Longchamp			#size-cells = <1>;
61fdc8c4adSValentin Longchamp			compatible = "fsl,ifc-nand";
62fdc8c4adSValentin Longchamp			reg = <0x1 0x0 0x10000>;
63fdc8c4adSValentin Longchamp		};
64fdc8c4adSValentin Longchamp
65fdc8c4adSValentin Longchamp		board-control@2,0 {
66fdc8c4adSValentin Longchamp			compatible = "keymile,qriox";
67fdc8c4adSValentin Longchamp			reg = <0x2 0x0 0x80>;
68fdc8c4adSValentin Longchamp		};
69fdc8c4adSValentin Longchamp
70fdc8c4adSValentin Longchamp		chassis-mgmt@6,0 {
71fdc8c4adSValentin Longchamp			compatible = "keymile,bfticu";
72fdc8c4adSValentin Longchamp			reg = <6 0 0x100>;
73fdc8c4adSValentin Longchamp			interrupt-controller;
74fdc8c4adSValentin Longchamp			interrupt-parent = <&mpic>;
75fdc8c4adSValentin Longchamp			interrupts = <11 1 0 0>;
76fdc8c4adSValentin Longchamp			#interrupt-cells = <1>;
77fdc8c4adSValentin Longchamp		};
78fdc8c4adSValentin Longchamp
79fdc8c4adSValentin Longchamp	};
80fdc8c4adSValentin Longchamp
81fdc8c4adSValentin Longchamp	memory {
82fdc8c4adSValentin Longchamp		device_type = "memory";
83fdc8c4adSValentin Longchamp	};
84fdc8c4adSValentin Longchamp
85fdc8c4adSValentin Longchamp	dcsr: dcsr@f00000000 {
86fdc8c4adSValentin Longchamp		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
87fdc8c4adSValentin Longchamp	};
88fdc8c4adSValentin Longchamp
89fdc8c4adSValentin Longchamp	bportals: bman-portals@ff4000000 {
90fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xf4000000 0x2000000>;
91fdc8c4adSValentin Longchamp	};
92fdc8c4adSValentin Longchamp
93fdc8c4adSValentin Longchamp	qportals: qman-portals@ff6000000 {
94fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xf6000000 0x2000000>;
95fdc8c4adSValentin Longchamp	};
96fdc8c4adSValentin Longchamp
97fdc8c4adSValentin Longchamp	soc: soc@ffe000000 {
98fdc8c4adSValentin Longchamp		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
99fdc8c4adSValentin Longchamp		reg = <0xf 0xfe000000 0 0x00001000>;
100fdc8c4adSValentin Longchamp
101fdc8c4adSValentin Longchamp		spi@110000 {
102fdc8c4adSValentin Longchamp			network-clock@1 {
103fdc8c4adSValentin Longchamp				compatible = "zarlink,zl30364";
104fdc8c4adSValentin Longchamp				reg = <1>;
105fdc8c4adSValentin Longchamp				spi-max-frequency = <1000000>;
106fdc8c4adSValentin Longchamp			};
107fdc8c4adSValentin Longchamp		};
108fdc8c4adSValentin Longchamp
109fdc8c4adSValentin Longchamp		sdhc@114000 {
110fdc8c4adSValentin Longchamp			status = "disabled";
111fdc8c4adSValentin Longchamp		};
112fdc8c4adSValentin Longchamp
113fdc8c4adSValentin Longchamp		i2c@118000 {
114fdc8c4adSValentin Longchamp			clock-frequency = <100000>;
115fdc8c4adSValentin Longchamp
116fdc8c4adSValentin Longchamp			mux@70 {
117fdc8c4adSValentin Longchamp				compatible = "nxp,pca9547";
118fdc8c4adSValentin Longchamp				reg = <0x70>;
119fdc8c4adSValentin Longchamp				#address-cells = <1>;
120fdc8c4adSValentin Longchamp				#size-cells = <0>;
121fdc8c4adSValentin Longchamp				i2c-mux-idle-disconnect;
122fdc8c4adSValentin Longchamp
123fdc8c4adSValentin Longchamp				i2c@0 {
124fdc8c4adSValentin Longchamp					reg = <0>;
125fdc8c4adSValentin Longchamp					#address-cells = <1>;
126fdc8c4adSValentin Longchamp					#size-cells = <0>;
127fdc8c4adSValentin Longchamp
128fdc8c4adSValentin Longchamp					eeprom@54 {
1296aeb4359SBartosz Golaszewski						compatible = "atmel,24c02";
130fdc8c4adSValentin Longchamp						reg = <0x54>;
131fdc8c4adSValentin Longchamp						pagesize = <2>;
132fdc8c4adSValentin Longchamp						read-only;
133fdc8c4adSValentin Longchamp						label = "ddr3-spd";
134fdc8c4adSValentin Longchamp					};
135fdc8c4adSValentin Longchamp				};
136fdc8c4adSValentin Longchamp
137fdc8c4adSValentin Longchamp				i2c@7 {
138fdc8c4adSValentin Longchamp					reg = <7>;
139fdc8c4adSValentin Longchamp					#address-cells = <1>;
140fdc8c4adSValentin Longchamp					#size-cells = <0>;
141fdc8c4adSValentin Longchamp
142fdc8c4adSValentin Longchamp					temp-sensor@48 {
143fdc8c4adSValentin Longchamp						compatible = "national,lm75";
144fdc8c4adSValentin Longchamp						reg = <0x48>;
145fdc8c4adSValentin Longchamp						label = "SENSOR_0";
146fdc8c4adSValentin Longchamp					};
147fdc8c4adSValentin Longchamp					temp-sensor@4a {
148fdc8c4adSValentin Longchamp						compatible = "national,lm75";
149fdc8c4adSValentin Longchamp						reg = <0x4a>;
150fdc8c4adSValentin Longchamp						label = "SENSOR_2";
151fdc8c4adSValentin Longchamp					};
152fdc8c4adSValentin Longchamp					temp-sensor@4b {
153fdc8c4adSValentin Longchamp						compatible = "national,lm75";
154fdc8c4adSValentin Longchamp						reg = <0x4b>;
155fdc8c4adSValentin Longchamp						label = "SENSOR_3";
156fdc8c4adSValentin Longchamp					};
157fdc8c4adSValentin Longchamp				};
158fdc8c4adSValentin Longchamp			};
159fdc8c4adSValentin Longchamp		};
160fdc8c4adSValentin Longchamp
161fdc8c4adSValentin Longchamp		i2c@118100 {
162fdc8c4adSValentin Longchamp			clock-frequency = <100000>;
163fdc8c4adSValentin Longchamp
164fdc8c4adSValentin Longchamp			eeprom@50 {
165fdc8c4adSValentin Longchamp				compatible = "atmel,24c08";
166fdc8c4adSValentin Longchamp				reg = <0x50>;
167fdc8c4adSValentin Longchamp				pagesize = <16>;
168fdc8c4adSValentin Longchamp			};
169fdc8c4adSValentin Longchamp
170fdc8c4adSValentin Longchamp			eeprom@54 {
171fdc8c4adSValentin Longchamp				compatible = "atmel,24c08";
172fdc8c4adSValentin Longchamp				reg = <0x54>;
173fdc8c4adSValentin Longchamp				pagesize = <16>;
174fdc8c4adSValentin Longchamp			};
175fdc8c4adSValentin Longchamp		};
176fdc8c4adSValentin Longchamp
177fdc8c4adSValentin Longchamp		i2c@119000 {
178fdc8c4adSValentin Longchamp			status = "disabled";
179fdc8c4adSValentin Longchamp		};
180fdc8c4adSValentin Longchamp
181fdc8c4adSValentin Longchamp		i2c@119100 {
182fdc8c4adSValentin Longchamp			status = "disabled";
183fdc8c4adSValentin Longchamp		};
184fdc8c4adSValentin Longchamp
185fdc8c4adSValentin Longchamp		serial2: serial@11d500 {
186fdc8c4adSValentin Longchamp			status = "disabled";
187fdc8c4adSValentin Longchamp		};
188fdc8c4adSValentin Longchamp
189fdc8c4adSValentin Longchamp		serial3: serial@11d600 {
190fdc8c4adSValentin Longchamp			status = "disabled";
191fdc8c4adSValentin Longchamp		};
192fdc8c4adSValentin Longchamp
193fdc8c4adSValentin Longchamp		usb0: usb@210000 {
194fdc8c4adSValentin Longchamp			status = "disabled";
195fdc8c4adSValentin Longchamp		};
196fdc8c4adSValentin Longchamp		usb1: usb@211000 {
197fdc8c4adSValentin Longchamp			status = "disabled";
198fdc8c4adSValentin Longchamp		};
199fdc8c4adSValentin Longchamp
200fdc8c4adSValentin Longchamp		display@180000 {
201fdc8c4adSValentin Longchamp			status = "disabled";
202fdc8c4adSValentin Longchamp		};
203fdc8c4adSValentin Longchamp
204fdc8c4adSValentin Longchamp		sata@220000 {
205fdc8c4adSValentin Longchamp			status = "disabled";
206fdc8c4adSValentin Longchamp		};
207fdc8c4adSValentin Longchamp		sata@221000 {
208fdc8c4adSValentin Longchamp			status = "disabled";
209fdc8c4adSValentin Longchamp		};
210fdc8c4adSValentin Longchamp
211fdc8c4adSValentin Longchamp		fman@400000 {
212fdc8c4adSValentin Longchamp			ethernet@e0000 {
213ea67a551SValentin Longchamp				phy-mode = "sgmii";
214ea67a551SValentin Longchamp				fixed-link {
215ea67a551SValentin Longchamp					speed = <1000>;
216ea67a551SValentin Longchamp					full-duplex;
217ea67a551SValentin Longchamp				};
218fdc8c4adSValentin Longchamp			};
219fdc8c4adSValentin Longchamp
220fdc8c4adSValentin Longchamp			ethernet@e2000 {
221ea67a551SValentin Longchamp				phy-mode = "sgmii";
222ea67a551SValentin Longchamp				fixed-link {
223ea67a551SValentin Longchamp					speed = <1000>;
224ea67a551SValentin Longchamp					full-duplex;
225ea67a551SValentin Longchamp				};
226fdc8c4adSValentin Longchamp			};
227fdc8c4adSValentin Longchamp
228fdc8c4adSValentin Longchamp			ethernet@e4000 {
229fdc8c4adSValentin Longchamp				status = "disabled";
230fdc8c4adSValentin Longchamp			};
231fdc8c4adSValentin Longchamp
232fdc8c4adSValentin Longchamp			ethernet@e6000 {
233fdc8c4adSValentin Longchamp				status = "disabled";
234fdc8c4adSValentin Longchamp			};
235fdc8c4adSValentin Longchamp
236fdc8c4adSValentin Longchamp			ethernet@e8000 {
237fdc8c4adSValentin Longchamp				phy-handle = <&front_phy>;
238ea67a551SValentin Longchamp				phy-mode = "rgmii-id";
239fdc8c4adSValentin Longchamp			};
240fdc8c4adSValentin Longchamp
241fdc8c4adSValentin Longchamp			mdio0: mdio@fc000 {
242fdc8c4adSValentin Longchamp				front_phy: ethernet-phy@11 {
243fdc8c4adSValentin Longchamp					reg = <0x11>;
244fdc8c4adSValentin Longchamp				};
245fdc8c4adSValentin Longchamp			};
246fdc8c4adSValentin Longchamp		};
247fdc8c4adSValentin Longchamp	};
248fdc8c4adSValentin Longchamp
249fdc8c4adSValentin Longchamp
250fdc8c4adSValentin Longchamp	pci0: pcie@ffe240000 {
251fdc8c4adSValentin Longchamp		reg = <0xf 0xfe240000 0 0x10000>;
252fdc8c4adSValentin Longchamp		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
253fdc8c4adSValentin Longchamp			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
254fdc8c4adSValentin Longchamp		pcie@0 {
255fdc8c4adSValentin Longchamp			ranges = <0x02000000 0 0xe0000000
256fdc8c4adSValentin Longchamp				  0x02000000 0 0xe0000000
257fdc8c4adSValentin Longchamp				  0 0x20000000
258fdc8c4adSValentin Longchamp
259fdc8c4adSValentin Longchamp				  0x01000000 0 0x00000000
260fdc8c4adSValentin Longchamp				  0x01000000 0 0x00000000
261fdc8c4adSValentin Longchamp				  0 0x00010000>;
262fdc8c4adSValentin Longchamp		};
263fdc8c4adSValentin Longchamp	};
264fdc8c4adSValentin Longchamp
265fdc8c4adSValentin Longchamp	pci1: pcie@ffe250000 {
266fdc8c4adSValentin Longchamp		status = "disabled";
267a76bea02SValentin Longchamp		reg = <0xf 0xfe250000 0 0x10000>;
268a76bea02SValentin Longchamp		ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
269a76bea02SValentin Longchamp			  0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
270a76bea02SValentin Longchamp		pcie@0 {
271a76bea02SValentin Longchamp			ranges = <0x02000000 0 0xe0000000
272a76bea02SValentin Longchamp				  0x02000000 0 0xe0000000
273a76bea02SValentin Longchamp				  0 0x10000000
274a76bea02SValentin Longchamp
275a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
276a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
277a76bea02SValentin Longchamp				  0 0x00010000>;
278a76bea02SValentin Longchamp		};
279fdc8c4adSValentin Longchamp	};
280fdc8c4adSValentin Longchamp
281fdc8c4adSValentin Longchamp	pci2: pcie@ffe260000 {
282fdc8c4adSValentin Longchamp		status = "disabled";
283a76bea02SValentin Longchamp		reg = <0xf 0xfe260000 0 0x10000>;
284a76bea02SValentin Longchamp		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
285a76bea02SValentin Longchamp			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
286a76bea02SValentin Longchamp		pcie@0 {
287a76bea02SValentin Longchamp			ranges = <0x02000000 0 0xe0000000
288a76bea02SValentin Longchamp				  0x02000000 0 0xe0000000
289a76bea02SValentin Longchamp				  0 0x10000000
290a76bea02SValentin Longchamp
291a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
292a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
293a76bea02SValentin Longchamp				  0 0x00010000>;
294a76bea02SValentin Longchamp		};
295fdc8c4adSValentin Longchamp	};
296fdc8c4adSValentin Longchamp
297fdc8c4adSValentin Longchamp	pci3: pcie@ffe270000 {
298fdc8c4adSValentin Longchamp		status = "disabled";
299a76bea02SValentin Longchamp		reg = <0xf 0xfe270000 0 0x10000>;
300a76bea02SValentin Longchamp		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
301a76bea02SValentin Longchamp			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
302a76bea02SValentin Longchamp		pcie@0 {
303a76bea02SValentin Longchamp			ranges = <0x02000000 0 0xe0000000
304a76bea02SValentin Longchamp				  0x02000000 0 0xe0000000
305a76bea02SValentin Longchamp				  0 0x10000000
306a76bea02SValentin Longchamp
307a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
308a76bea02SValentin Longchamp				  0x01000000 0 0x00000000
309a76bea02SValentin Longchamp				  0 0x00010000>;
310a76bea02SValentin Longchamp		};
311fdc8c4adSValentin Longchamp	};
312fdc8c4adSValentin Longchamp
313fdc8c4adSValentin Longchamp	qe: qe@ffe140000 {
314fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xfe140000 0x40000>;
315fdc8c4adSValentin Longchamp		reg = <0xf 0xfe140000 0 0x480>;
316fdc8c4adSValentin Longchamp		brg-frequency = <0>;
317fdc8c4adSValentin Longchamp		bus-frequency = <0>;
318fdc8c4adSValentin Longchamp
319fdc8c4adSValentin Longchamp		si1: si@700 {
320fdc8c4adSValentin Longchamp			compatible = "fsl,t1040-qe-si";
321fdc8c4adSValentin Longchamp			reg = <0x700 0x80>;
322fdc8c4adSValentin Longchamp		};
323fdc8c4adSValentin Longchamp
324fdc8c4adSValentin Longchamp		siram1: siram@1000 {
325fdc8c4adSValentin Longchamp			compatible = "fsl,t1040-qe-siram";
326fdc8c4adSValentin Longchamp			reg = <0x1000 0x800>;
327fdc8c4adSValentin Longchamp		};
328fdc8c4adSValentin Longchamp
329fdc8c4adSValentin Longchamp		ucc_hdlc: ucc@2000 {
330fdc8c4adSValentin Longchamp			device_type = "hdlc";
331fdc8c4adSValentin Longchamp			compatible = "fsl,ucc-hdlc";
332fdc8c4adSValentin Longchamp			rx-clock-name = "clk9";
333fdc8c4adSValentin Longchamp			tx-clock-name = "clk9";
3341f6753d6SHolger Brunck			fsl,hdlc-bus;
335fdc8c4adSValentin Longchamp		};
336fdc8c4adSValentin Longchamp	};
337fdc8c4adSValentin Longchamp};
338fdc8c4adSValentin Longchamp
339fdc8c4adSValentin Longchamp#include "t1040si-post.dtsi"
340