1/*
2 * GE SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
20
21/dts-v1/;
22
23/ {
24	model = "GEF_SBC310";
25	compatible = "gef,sbc310";
26	#address-cells = <1>;
27	#size-cells = <1>;
28	interrupt-parent = <&mpic>;
29
30	aliases {
31		ethernet0 = &enet0;
32		ethernet1 = &enet1;
33		serial0 = &serial0;
34		serial1 = &serial1;
35		pci0 = &pci0;
36		pci1 = &pci1;
37	};
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42
43		PowerPC,8641@0 {
44			device_type = "cpu";
45			reg = <0>;
46			d-cache-line-size = <32>;	// 32 bytes
47			i-cache-line-size = <32>;	// 32 bytes
48			d-cache-size = <32768>;		// L1, 32K
49			i-cache-size = <32768>;		// L1, 32K
50			timebase-frequency = <0>;	// From uboot
51			bus-frequency = <0>;		// From uboot
52			clock-frequency = <0>;		// From uboot
53		};
54		PowerPC,8641@1 {
55			device_type = "cpu";
56			reg = <1>;
57			d-cache-line-size = <32>;	// 32 bytes
58			i-cache-line-size = <32>;	// 32 bytes
59			d-cache-size = <32768>;		// L1, 32K
60			i-cache-size = <32768>;		// L1, 32K
61			timebase-frequency = <0>;	// From uboot
62			bus-frequency = <0>;		// From uboot
63			clock-frequency = <0>;		// From uboot
64		};
65	};
66
67	memory {
68		device_type = "memory";
69		reg = <0x0 0x40000000>;	// set by uboot
70	};
71
72	localbus@fef05000 {
73		#address-cells = <2>;
74		#size-cells = <1>;
75		compatible = "fsl,mpc8641-localbus", "simple-bus";
76		reg = <0xfef05000 0x1000>;
77		interrupts = <19 2 0 0>;
78
79		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
80			  1 0 0xe0000000 0x08000000	// Paged Flash 0
81			  2 0 0xe8000000 0x08000000	// Paged Flash 1
82			  3 0 0xfc100000 0x00020000	// NVRAM
83			  4 0 0xfc000000 0x00010000>;	// FPGA
84
85		/* flash@0,0 is a mirror of part of the memory in flash@1,0
86		flash@0,0 {
87			compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
88			reg = <0x0 0x0 0x01000000>;
89			bank-width = <2>;
90			device-width = <2>;
91			#address-cells = <1>;
92			#size-cells = <1>;
93			partition@0 {
94				label = "firmware";
95				reg = <0x0 0x01000000>;
96				read-only;
97			};
98		};
99		*/
100
101		flash@1,0 {
102			compatible = "gef,sbc310-paged-flash", "cfi-flash";
103			reg = <0x1 0x0 0x8000000>;
104			bank-width = <2>;
105			device-width = <2>;
106			#address-cells = <1>;
107			#size-cells = <1>;
108			partition@0 {
109				label = "user";
110				reg = <0x0 0x7800000>;
111			};
112			partition@7800000 {
113				label = "firmware";
114				reg = <0x7800000 0x800000>;
115				read-only;
116			};
117		};
118
119		nvram@3,0 {
120			device_type = "nvram";
121			compatible = "simtek,stk14ca8";
122			reg = <0x3 0x0 0x20000>;
123		};
124
125		fpga@4,0 {
126			compatible = "gef,fpga-regs";
127			reg = <0x4 0x0 0x40>;
128		};
129
130		wdt@4,2000 {
131			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
132				"gef,fpga-wdt";
133			reg = <0x4 0x2000 0x8>;
134			interrupts = <0x1a 0x4>;
135			interrupt-parent = <&gef_pic>;
136		};
137/*
138		wdt@4,2010 {
139			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
140				"gef,fpga-wdt";
141			reg = <0x4 0x2010 0x8>;
142			interrupts = <0x1b 0x4>;
143			interrupt-parent = <&gef_pic>;
144		};
145*/
146		gef_pic: pic@4,4000 {
147			#interrupt-cells = <1>;
148			interrupt-controller;
149			compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
150			reg = <0x4 0x4000 0x20>;
151			interrupts = <0x8 0x9 0 0>;
152
153		};
154		gef_gpio: gpio@4,8000 {
155			#gpio-cells = <2>;
156			compatible = "gef,sbc310-gpio";
157			reg = <0x4 0x8000 0x24>;
158			gpio-controller;
159		};
160	};
161
162	soc@fef00000 {
163		#address-cells = <1>;
164		#size-cells = <1>;
165		device_type = "soc";
166		compatible = "fsl,mpc8641-soc", "simple-bus";
167		ranges = <0x0 0xfef00000 0x00100000>;
168		bus-frequency = <33333333>;
169
170		mcm-law@0 {
171			compatible = "fsl,mcm-law";
172			reg = <0x0 0x1000>;
173			fsl,num-laws = <10>;
174		};
175
176		mcm@1000 {
177			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
178			reg = <0x1000 0x1000>;
179			interrupts = <17 2 0 0>;
180		};
181
182		i2c@3000 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			compatible = "fsl-i2c";
186			reg = <0x3000 0x100>;
187			interrupts = <0x2b 0x2 0 0>;
188			dfsrr;
189
190			rtc@51 {
191				compatible = "epson,rx8581";
192				reg = <0x00000051>;
193			};
194		};
195
196		i2c@3100 {
197			#address-cells = <1>;
198			#size-cells = <0>;
199			compatible = "fsl-i2c";
200			reg = <0x3100 0x100>;
201			interrupts = <0x2b 0x2 0 0>;
202			dfsrr;
203
204			hwmon@48 {
205				compatible = "national,lm92";
206				reg = <0x48>;
207			};
208
209			hwmon@4c {
210				compatible = "adi,adt7461";
211				reg = <0x4c>;
212			};
213
214			eti@6b {
215				compatible = "dallas,ds1682";
216				reg = <0x6b>;
217			};
218		};
219
220		dma@21300 {
221			#address-cells = <1>;
222			#size-cells = <1>;
223			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
224			reg = <0x21300 0x4>;
225			ranges = <0x0 0x21100 0x200>;
226			cell-index = <0>;
227			dma-channel@0 {
228				compatible = "fsl,mpc8641-dma-channel",
229					   "fsl,eloplus-dma-channel";
230				reg = <0x0 0x80>;
231				cell-index = <0>;
232				interrupts = <20 2 0 0>;
233			};
234			dma-channel@80 {
235				compatible = "fsl,mpc8641-dma-channel",
236					   "fsl,eloplus-dma-channel";
237				reg = <0x80 0x80>;
238				cell-index = <1>;
239				interrupts = <21 2 0 0>;
240			};
241			dma-channel@100 {
242				compatible = "fsl,mpc8641-dma-channel",
243					   "fsl,eloplus-dma-channel";
244				reg = <0x100 0x80>;
245				cell-index = <2>;
246				interrupts = <22 2 0 0>;
247			};
248			dma-channel@180 {
249				compatible = "fsl,mpc8641-dma-channel",
250					   "fsl,eloplus-dma-channel";
251				reg = <0x180 0x80>;
252				cell-index = <3>;
253				interrupts = <23 2 0 0>;
254			};
255		};
256
257		enet0: ethernet@24000 {
258			#address-cells = <1>;
259			#size-cells = <1>;
260			cell-index = <0>;
261			device_type = "network";
262			model = "TSEC";
263			compatible = "gianfar";
264			reg = <0x24000 0x1000>;
265			ranges = <0x0 0x24000 0x1000>;
266			local-mac-address = [ 00 00 00 00 00 00 ];
267			interrupts = <29 2 0 0 30  2 0 0 34 2 0 0>;
268			tbi-handle = <&tbi0>;
269			phy-handle = <&phy0>;
270			phy-connection-type = "gmii";
271
272			mdio@520 {
273				#address-cells = <1>;
274				#size-cells = <0>;
275				compatible = "fsl,gianfar-mdio";
276				reg = <0x520 0x20>;
277
278				phy0: ethernet-phy@0 {
279					interrupt-parent = <&gef_pic>;
280					interrupts = <0x9 0x4>;
281					reg = <1>;
282				};
283				phy2: ethernet-phy@2 {
284					interrupt-parent = <&gef_pic>;
285					interrupts = <0x8 0x4>;
286					reg = <3>;
287				};
288				tbi0: tbi-phy@11 {
289					reg = <0x11>;
290					device_type = "tbi-phy";
291				};
292			};
293		};
294
295		enet1: ethernet@26000 {
296			#address-cells = <1>;
297			#size-cells = <1>;
298			cell-index = <2>;
299			device_type = "network";
300			model = "TSEC";
301			compatible = "gianfar";
302			reg = <0x26000 0x1000>;
303			ranges = <0x0 0x26000 0x1000>;
304			local-mac-address = [ 00 00 00 00 00 00 ];
305			interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
306			tbi-handle = <&tbi2>;
307			phy-handle = <&phy2>;
308			phy-connection-type = "gmii";
309
310			mdio@520 {
311				#address-cells = <1>;
312				#size-cells = <0>;
313				compatible = "fsl,gianfar-tbi";
314				reg = <0x520 0x20>;
315
316				tbi2: tbi-phy@11 {
317					reg = <0x11>;
318					device_type = "tbi-phy";
319				};
320			};
321		};
322
323		serial0: serial@4500 {
324			cell-index = <0>;
325			device_type = "serial";
326			compatible = "fsl,ns16550", "ns16550";
327			reg = <0x4500 0x100>;
328			clock-frequency = <0>;
329			interrupts = <0x2a 0x2 0 0>;
330		};
331
332		serial1: serial@4600 {
333			cell-index = <1>;
334			device_type = "serial";
335			compatible = "fsl,ns16550", "ns16550";
336			reg = <0x4600 0x100>;
337			clock-frequency = <0>;
338			interrupts = <0x1c 0x2 0 0>;
339		};
340
341		mpic: pic@40000 {
342			clock-frequency = <0>;
343			interrupt-controller;
344			#address-cells = <0>;
345			#interrupt-cells = <4>;
346			reg = <0x40000 0x40000>;
347			compatible = "fsl,mpic", "chrp,open-pic";
348			device_type = "open-pic";
349		};
350
351		msi@41600 {
352			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
353			reg = <0x41600 0x80>;
354			msi-available-ranges = <0 0x100>;
355			interrupts = <
356				0xe0 0 0 0
357				0xe1 0 0 0
358				0xe2 0 0 0
359				0xe3 0 0 0
360				0xe4 0 0 0
361				0xe5 0 0 0
362				0xe6 0 0 0
363				0xe7 0 0 0>;
364		};
365
366		global-utilities@e0000 {
367			compatible = "fsl,mpc8641-guts";
368			reg = <0xe0000 0x1000>;
369			fsl,has-rstcr;
370		};
371	};
372
373	pci0: pcie@fef08000 {
374		compatible = "fsl,mpc8641-pcie";
375		device_type = "pci";
376		#size-cells = <2>;
377		#address-cells = <3>;
378		reg = <0xfef08000 0x1000>;
379		bus-range = <0x0 0xff>;
380		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
381			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
382		clock-frequency = <100000000>;
383		interrupts = <0x18 0x2 0 0>;
384		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
385		interrupt-map = <
386			0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
387			0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
388			0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
389			0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
390		>;
391
392		pcie@0 {
393			reg = <0 0 0 0 0>;
394			#size-cells = <2>;
395			#address-cells = <3>;
396			device_type = "pci";
397			ranges = <0x02000000 0x0 0x80000000
398				  0x02000000 0x0 0x80000000
399				  0x0 0x40000000
400
401				  0x01000000 0x0 0x00000000
402				  0x01000000 0x0 0x00000000
403				  0x0 0x00400000>;
404		};
405	};
406
407	pci1: pcie@fef09000 {
408		compatible = "fsl,mpc8641-pcie";
409		device_type = "pci";
410		#size-cells = <2>;
411		#address-cells = <3>;
412		reg = <0xfef09000 0x1000>;
413		bus-range = <0x0 0xff>;
414		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
415			  0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
416		clock-frequency = <100000000>;
417		interrupts = <0x19 0x2 0 0>;
418		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
419		interrupt-map = <
420			0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
421			0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
422			0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
423			0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
424			>;
425
426		pcie@0 {
427			reg = <0 0 0 0 0>;
428			#size-cells = <2>;
429			#address-cells = <3>;
430			device_type = "pci";
431			ranges = <0x02000000 0x0 0xc0000000
432				  0x02000000 0x0 0xc0000000
433				  0x0 0x20000000
434
435				  0x01000000 0x0 0x00000000
436				  0x01000000 0x0 0x00000000
437				  0x0 0x00400000>;
438		};
439	};
440};
441