1/* 2 * GE SBC310 Device Tree Source 3 * 4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Based on: SBS CM6 Device Tree Source 12 * Copyright 2007 SBS Technologies GmbH & Co. KG 13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) 14 * Copyright 2006 Freescale Semiconductor Inc. 15 */ 16 17/* 18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts 19 */ 20 21/include/ "mpc8641si-pre.dtsi" 22 23/ { 24 model = "GEF_SBC310"; 25 compatible = "gef,sbc310"; 26 27 aliases { 28 pci1 = &pci1; 29 }; 30 31 memory { 32 device_type = "memory"; 33 reg = <0x0 0x40000000>; // set by uboot 34 }; 35 36 lbc: localbus@fef05000 { 37 reg = <0xfef05000 0x1000>; 38 39 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 40 1 0 0xe0000000 0x08000000 // Paged Flash 0 41 2 0 0xe8000000 0x08000000 // Paged Flash 1 42 3 0 0xfc100000 0x00020000 // NVRAM 43 4 0 0xfc000000 0x00010000>; // FPGA 44 45 /* flash@0,0 is a mirror of part of the memory in flash@1,0 46 flash@0,0 { 47 compatible = "gef,sbc310-firmware-mirror", "cfi-flash"; 48 reg = <0x0 0x0 0x01000000>; 49 bank-width = <2>; 50 device-width = <2>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 partition@0 { 54 label = "firmware"; 55 reg = <0x0 0x01000000>; 56 read-only; 57 }; 58 }; 59 */ 60 61 flash@1,0 { 62 compatible = "gef,sbc310-paged-flash", "cfi-flash"; 63 reg = <0x1 0x0 0x8000000>; 64 bank-width = <2>; 65 device-width = <2>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 partition@0 { 69 label = "user"; 70 reg = <0x0 0x7800000>; 71 }; 72 partition@7800000 { 73 label = "firmware"; 74 reg = <0x7800000 0x800000>; 75 read-only; 76 }; 77 }; 78 79 nvram@3,0 { 80 device_type = "nvram"; 81 compatible = "simtek,stk14ca8"; 82 reg = <0x3 0x0 0x20000>; 83 }; 84 85 fpga@4,0 { 86 compatible = "gef,fpga-regs"; 87 reg = <0x4 0x0 0x40>; 88 }; 89 90 wdt@4,2000 { 91 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", 92 "gef,fpga-wdt"; 93 reg = <0x4 0x2000 0x8>; 94 interrupts = <0x1a 0x4>; 95 interrupt-parent = <&gef_pic>; 96 }; 97/* 98 wdt@4,2010 { 99 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", 100 "gef,fpga-wdt"; 101 reg = <0x4 0x2010 0x8>; 102 interrupts = <0x1b 0x4>; 103 interrupt-parent = <&gef_pic>; 104 }; 105*/ 106 gef_pic: pic@4,4000 { 107 #interrupt-cells = <1>; 108 interrupt-controller; 109 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic"; 110 reg = <0x4 0x4000 0x20>; 111 interrupts = <0x8 0x9 0 0>; 112 113 }; 114 gef_gpio: gpio@4,8000 { 115 #gpio-cells = <2>; 116 compatible = "gef,sbc310-gpio"; 117 reg = <0x4 0x8000 0x24>; 118 gpio-controller; 119 }; 120 }; 121 122 soc: soc@fef00000 { 123 ranges = <0x0 0xfef00000 0x00100000>; 124 125 i2c@3000 { 126 rtc@51 { 127 compatible = "epson,rx8581"; 128 reg = <0x00000051>; 129 }; 130 }; 131 132 i2c@3100 { 133 hwmon@48 { 134 compatible = "national,lm92"; 135 reg = <0x48>; 136 }; 137 138 hwmon@4c { 139 compatible = "adi,adt7461"; 140 reg = <0x4c>; 141 }; 142 143 eti@6b { 144 compatible = "dallas,ds1682"; 145 reg = <0x6b>; 146 }; 147 }; 148 149 enet0: ethernet@24000 { 150 tbi-handle = <&tbi0>; 151 phy-handle = <&phy0>; 152 phy-connection-type = "gmii"; 153 }; 154 155 mdio@24520 { 156 phy0: ethernet-phy@0 { 157 interrupt-parent = <&gef_pic>; 158 interrupts = <0x9 0x4>; 159 reg = <1>; 160 }; 161 phy2: ethernet-phy@2 { 162 interrupt-parent = <&gef_pic>; 163 interrupts = <0x8 0x4>; 164 reg = <3>; 165 }; 166 tbi0: tbi-phy@11 { 167 reg = <0x11>; 168 device_type = "tbi-phy"; 169 }; 170 }; 171 172 enet1: ethernet@26000 { 173 tbi-handle = <&tbi2>; 174 phy-handle = <&phy2>; 175 phy-connection-type = "gmii"; 176 }; 177 178 mdio@26520 { 179 tbi2: tbi-phy@11 { 180 reg = <0x11>; 181 device_type = "tbi-phy"; 182 }; 183 }; 184 185 enet2: ethernet@25000 { 186 status = "disabled"; 187 }; 188 189 mdio@25520 { 190 status = "disabled"; 191 }; 192 193 enet3: ethernet@27000 { 194 status = "disabled"; 195 }; 196 197 mdio@27520 { 198 status = "disabled"; 199 }; 200 }; 201 202 pci0: pcie@fef08000 { 203 reg = <0xfef08000 0x1000>; 204 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 205 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 206 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 207 interrupt-map = < 208 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 209 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 210 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 211 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 212 >; 213 214 pcie@0 { 215 ranges = <0x02000000 0x0 0x80000000 216 0x02000000 0x0 0x80000000 217 0x0 0x40000000 218 219 0x01000000 0x0 0x00000000 220 0x01000000 0x0 0x00000000 221 0x0 0x00400000>; 222 }; 223 }; 224 225 pci1: pcie@fef09000 { 226 compatible = "fsl,mpc8641-pcie"; 227 device_type = "pci"; 228 #size-cells = <2>; 229 #address-cells = <3>; 230 reg = <0xfef09000 0x1000>; 231 bus-range = <0x0 0xff>; 232 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 233 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>; 234 clock-frequency = <100000000>; 235 interrupts = <0x19 0x2 0 0>; 236 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 237 interrupt-map = < 238 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2 239 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2 240 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2 241 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2 242 >; 243 244 pcie@0 { 245 reg = <0 0 0 0 0>; 246 #size-cells = <2>; 247 #address-cells = <3>; 248 device_type = "pci"; 249 ranges = <0x02000000 0x0 0xc0000000 250 0x02000000 0x0 0xc0000000 251 0x0 0x20000000 252 253 0x01000000 0x0 0x00000000 254 0x01000000 0x0 0x00000000 255 0x0 0x00400000>; 256 }; 257 }; 258}; 259 260/include/ "mpc8641si-post.dtsi" 261