1/* 2 * B4420 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2012 - 2014 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of 32 * this software, even if advised of the possibility of such damage. 33 */ 34 35&bman_fbpr { 36 compatible = "fsl,bman-fbpr"; 37 alloc-ranges = <0 0 0x10000 0>; 38}; 39 40&ifc { 41 #address-cells = <2>; 42 #size-cells = <1>; 43 compatible = "fsl,ifc", "simple-bus"; 44 interrupts = <25 2 0 0>; 45}; 46 47/* controller at 0x200000 */ 48&pci0 { 49 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4"; 50 device_type = "pci"; 51 #size-cells = <2>; 52 #address-cells = <3>; 53 bus-range = <0x0 0xff>; 54 interrupts = <20 2 0 0>; 55 fsl,iommu-parent = <&pamu0>; 56 pcie@0 { 57 #interrupt-cells = <1>; 58 #size-cells = <2>; 59 #address-cells = <3>; 60 device_type = "pci"; 61 reg = <0 0 0 0 0>; 62 interrupts = <20 2 0 0>; 63 interrupt-map-mask = <0xf800 0 0 7>; 64 interrupt-map = < 65 /* IDSEL 0x0 */ 66 0000 0 0 1 &mpic 40 1 0 0 67 0000 0 0 2 &mpic 1 1 0 0 68 0000 0 0 3 &mpic 2 1 0 0 69 0000 0 0 4 &mpic 3 1 0 0 70 >; 71 }; 72}; 73 74&dcsr { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,dcsr", "simple-bus"; 78 79 dcsr-epu@0 { 80 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu"; 81 interrupts = <52 2 0 0 82 84 2 0 0 83 85 2 0 0 84 94 2 0 0 85 95 2 0 0>; 86 reg = <0x0 0x1000>; 87 }; 88 dcsr-npc { 89 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc"; 90 reg = <0x1000 0x1000 0x1002000 0x10000>; 91 }; 92 dcsr-nxc@2000 { 93 compatible = "fsl,dcsr-nxc"; 94 reg = <0x2000 0x1000>; 95 }; 96 dcsr-corenet { 97 compatible = "fsl,dcsr-corenet"; 98 reg = <0x8000 0x1000 0x1A000 0x1000>; 99 }; 100 dcsr-dpaa@9000 { 101 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa"; 102 reg = <0x9000 0x1000>; 103 }; 104 dcsr-ocn@11000 { 105 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn"; 106 reg = <0x11000 0x1000>; 107 }; 108 dcsr-ddr@12000 { 109 compatible = "fsl,dcsr-ddr"; 110 dev-handle = <&ddr1>; 111 reg = <0x12000 0x1000>; 112 }; 113 dcsr-nal@18000 { 114 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal"; 115 reg = <0x18000 0x1000>; 116 }; 117 dcsr-rcpm@22000 { 118 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm"; 119 reg = <0x22000 0x1000>; 120 }; 121 dcsr-snpc@30000 { 122 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; 123 reg = <0x30000 0x1000 0x1022000 0x10000>; 124 }; 125 dcsr-snpc@31000 { 126 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; 127 reg = <0x31000 0x1000 0x1042000 0x10000>; 128 }; 129 dcsr-cpu-sb-proxy@100000 { 130 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 131 cpu-handle = <&cpu0>; 132 reg = <0x100000 0x1000 0x101000 0x1000>; 133 }; 134}; 135 136&bportals { 137 #address-cells = <0x1>; 138 #size-cells = <0x1>; 139 compatible = "simple-bus"; 140 141 bman-portal@0 { 142 compatible = "fsl,bman-portal"; 143 reg = <0x0 0x4000>, <0x1000000 0x1000>; 144 interrupts = <105 2 0 0>; 145 }; 146 bman-portal@4000 { 147 compatible = "fsl,bman-portal"; 148 reg = <0x4000 0x4000>, <0x1001000 0x1000>; 149 interrupts = <107 2 0 0>; 150 }; 151 bman-portal@8000 { 152 compatible = "fsl,bman-portal"; 153 reg = <0x8000 0x4000>, <0x1002000 0x1000>; 154 interrupts = <109 2 0 0>; 155 }; 156 bman-portal@c000 { 157 compatible = "fsl,bman-portal"; 158 reg = <0xc000 0x4000>, <0x1003000 0x1000>; 159 interrupts = <111 2 0 0>; 160 }; 161 bman-portal@10000 { 162 compatible = "fsl,bman-portal"; 163 reg = <0x10000 0x4000>, <0x1004000 0x1000>; 164 interrupts = <113 2 0 0>; 165 }; 166 bman-portal@14000 { 167 compatible = "fsl,bman-portal"; 168 reg = <0x14000 0x4000>, <0x1005000 0x1000>; 169 interrupts = <115 2 0 0>; 170 }; 171 bman-portal@18000 { 172 compatible = "fsl,bman-portal"; 173 reg = <0x18000 0x4000>, <0x1006000 0x1000>; 174 interrupts = <117 2 0 0>; 175 }; 176 bman-portal@1c000 { 177 compatible = "fsl,bman-portal"; 178 reg = <0x1c000 0x4000>, <0x1007000 0x1000>; 179 interrupts = <119 2 0 0>; 180 }; 181 bman-portal@20000 { 182 compatible = "fsl,bman-portal"; 183 reg = <0x20000 0x4000>, <0x1008000 0x1000>; 184 interrupts = <121 2 0 0>; 185 }; 186 bman-portal@24000 { 187 compatible = "fsl,bman-portal"; 188 reg = <0x24000 0x4000>, <0x1009000 0x1000>; 189 interrupts = <123 2 0 0>; 190 }; 191 bman-portal@28000 { 192 compatible = "fsl,bman-portal"; 193 reg = <0x28000 0x4000>, <0x100a000 0x1000>; 194 interrupts = <125 2 0 0>; 195 }; 196 bman-portal@2c000 { 197 compatible = "fsl,bman-portal"; 198 reg = <0x2c000 0x4000>, <0x100b000 0x1000>; 199 interrupts = <127 2 0 0>; 200 }; 201 bman-portal@30000 { 202 compatible = "fsl,bman-portal"; 203 reg = <0x30000 0x4000>, <0x100c000 0x1000>; 204 interrupts = <129 2 0 0>; 205 }; 206 bman-portal@34000 { 207 compatible = "fsl,bman-portal"; 208 reg = <0x34000 0x4000>, <0x100d000 0x1000>; 209 interrupts = <131 2 0 0>; 210 }; 211}; 212 213&soc { 214 #address-cells = <1>; 215 #size-cells = <1>; 216 device_type = "soc"; 217 compatible = "simple-bus"; 218 219 soc-sram-error { 220 compatible = "fsl,soc-sram-error"; 221 interrupts = <16 2 1 2>; 222 }; 223 224 corenet-law@0 { 225 compatible = "fsl,corenet-law"; 226 reg = <0x0 0x1000>; 227 fsl,num-laws = <32>; 228 }; 229 230 ddr1: memory-controller@8000 { 231 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 232 reg = <0x8000 0x1000>; 233 interrupts = <16 2 1 8>; 234 }; 235 236 cpc: l3-cache-controller@10000 { 237 compatible = "fsl,b4-l3-cache-controller", "cache"; 238 reg = <0x10000 0x1000>; 239 interrupts = <16 2 1 4>; 240 }; 241 242 corenet-cf@18000 { 243 compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; 244 reg = <0x18000 0x1000>; 245 interrupts = <16 2 1 0>; 246 fsl,ccf-num-csdids = <32>; 247 fsl,ccf-num-snoopids = <32>; 248 }; 249 250 iommu@20000 { 251 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 252 reg = <0x20000 0x4000>; 253 fsl,portid-mapping = <0x8000>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 interrupts = < 257 24 2 0 0 258 16 2 1 1>; 259 260 261 /* PCIe, DMA, SRIO */ 262 pamu0: pamu@0 { 263 reg = <0 0x1000>; 264 fsl,primary-cache-geometry = <8 1>; 265 fsl,secondary-cache-geometry = <32 2>; 266 }; 267 268 /* AXI2, Maple */ 269 pamu1: pamu@1000 { 270 reg = <0x1000 0x1000>; 271 fsl,primary-cache-geometry = <32 1>; 272 fsl,secondary-cache-geometry = <32 2>; 273 }; 274 275 /* Q/BMan */ 276 pamu2: pamu@2000 { 277 reg = <0x2000 0x1000>; 278 fsl,primary-cache-geometry = <32 1>; 279 fsl,secondary-cache-geometry = <32 2>; 280 }; 281 282 /* AXI1, FMAN */ 283 pamu3: pamu@3000 { 284 reg = <0x3000 0x1000>; 285 fsl,primary-cache-geometry = <32 1>; 286 fsl,secondary-cache-geometry = <32 2>; 287 }; 288 }; 289 290/include/ "qoriq-mpic4.3.dtsi" 291 292 guts: global-utilities@e0000 { 293 compatible = "fsl,b4-device-config"; 294 reg = <0xe0000 0xe00>; 295 fsl,has-rstcr; 296 fsl,liodn-bits = <12>; 297 }; 298 299 clockgen: global-utilities@e1000 { 300 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0"; 301 reg = <0xe1000 0x1000>; 302 }; 303 304 rcpm: global-utilities@e2000 { 305 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0"; 306 reg = <0xe2000 0x1000>; 307 }; 308 309/include/ "elo3-dma-0.dtsi" 310 dma@100300 { 311 fsl,iommu-parent = <&pamu0>; 312 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ 313 }; 314 315/include/ "elo3-dma-1.dtsi" 316 dma@101300 { 317 fsl,iommu-parent = <&pamu0>; 318 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ 319 }; 320 321/include/ "qonverge-usb2-dr-0.dtsi" 322 usb0: usb@210000 { 323 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 324 fsl,iommu-parent = <&pamu1>; 325 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 326 }; 327 328/include/ "qoriq-espi-0.dtsi" 329 spi@110000 { 330 fsl,espi-num-chipselects = <4>; 331 }; 332 333/include/ "qoriq-esdhc-0.dtsi" 334 sdhc@114000 { 335 sdhci,auto-cmd12; 336 fsl,iommu-parent = <&pamu1>; 337 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 338 }; 339 340/include/ "qoriq-i2c-0.dtsi" 341/include/ "qoriq-i2c-1.dtsi" 342/include/ "qoriq-duart-0.dtsi" 343/include/ "qoriq-duart-1.dtsi" 344/include/ "qoriq-sec5.3-0.dtsi" 345 346/include/ "qoriq-bman1.dtsi" 347 bman: bman@31a000 { 348 interrupts = <16 2 1 29>; 349 }; 350 351 L2: l2-cache-controller@c20000 { 352 compatible = "fsl,b4-l2-cache-controller"; 353 reg = <0xc20000 0x1000>; 354 next-level-cache = <&cpc>; 355 }; 356}; 357