1/*
2 * B4420 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/include/ "b4si-post.dtsi"
36
37/* controller at 0x200000 */
38&pci0 {
39	compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
40};
41
42&dcsr {
43	dcsr-epu@0 {
44		compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
45	};
46	dcsr-npc {
47		compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
48	};
49	dcsr-dpaa@9000 {
50		compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
51	};
52	dcsr-ocn@11000 {
53		compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
54	};
55	dcsr-nal@18000 {
56		compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
57	};
58	dcsr-rcpm@22000 {
59		compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
60	};
61	dcsr-snpc@30000 {
62		compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
63	};
64	dcsr-snpc@31000 {
65		compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
66	};
67	dcsr-cpu-sb-proxy@108000 {
68		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
69		cpu-handle = <&cpu1>;
70		reg = <0x108000 0x1000 0x109000 0x1000>;
71	};
72};
73
74&soc {
75	cpc: l3-cache-controller@10000 {
76		compatible = "fsl,b4420-l3-cache-controller", "cache";
77	};
78
79	corenet-cf@18000 {
80		compatible = "fsl,b4420-corenet-cf";
81	};
82
83	guts: global-utilities@e0000 {
84		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85	};
86
87	clockgen: global-utilities@e1000 {
88		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
89		ranges = <0x0 0xe1000 0x1000>;
90		#address-cells = <1>;
91		#size-cells = <1>;
92
93		sysclk: sysclk {
94			#clock-cells = <0>;
95			compatible = "fsl,qoriq-sysclk-2.0";
96			clock-output-names = "sysclk";
97		};
98
99		pll0: pll0@800 {
100			#clock-cells = <1>;
101			reg = <0x800 0x4>;
102			compatible = "fsl,qoriq-core-pll-2.0";
103			clocks = <&sysclk>;
104			clock-output-names = "pll0", "pll0-div2", "pll0-div4";
105		};
106
107		pll1: pll1@820 {
108			#clock-cells = <1>;
109			reg = <0x820 0x4>;
110			compatible = "fsl,qoriq-core-pll-2.0";
111			clocks = <&sysclk>;
112			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
113		};
114
115		mux0: mux0@0 {
116			#clock-cells = <0>;
117			reg = <0x0 0x4>;
118			compatible = "fsl,qoriq-core-mux-2.0";
119			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
120				<&pll1 0>, <&pll1 1>, <&pll1 2>;
121			clock-names = "pll0", "pll0-div2", "pll0-div4",
122				"pll1", "pll1-div2", "pll1-div4";
123			clock-output-names = "cmux0";
124		};
125	};
126
127	rcpm: global-utilities@e2000 {
128		compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
129	};
130
131	L2: l2-cache-controller@c20000 {
132		compatible = "fsl,b4420-l2-cache-controller";
133	};
134};
135