1/* 2 * Device Tree Source for IBM Ebony 3 * 4 * Copyright (c) 2006, 2007 IBM Corp. 5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 6 * 7 * FIXME: Draft only! 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without 11 * any warranty of any kind, whether express or implied. 12 */ 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <1>; 17 model = "ibm,ebony"; 18 compatible = "ibm,ebony"; 19 dcr-parent = <&/cpus/PowerPC,440GP@0>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 PowerPC,440GP@0 { 26 device_type = "cpu"; 27 reg = <0>; 28 clock-frequency = <0>; // Filled in by zImage 29 timebase-frequency = <0>; // Filled in by zImage 30 i-cache-line-size = <20>; 31 d-cache-line-size = <20>; 32 i-cache-size = <8000>; /* 32 kB */ 33 d-cache-size = <8000>; /* 32 kB */ 34 dcr-controller; 35 dcr-access-method = "native"; 36 }; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0 0 0>; // Filled in by zImage 42 }; 43 44 UIC0: interrupt-controller0 { 45 compatible = "ibm,uic-440gp", "ibm,uic"; 46 interrupt-controller; 47 cell-index = <0>; 48 dcr-reg = <0c0 009>; 49 #address-cells = <0>; 50 #size-cells = <0>; 51 #interrupt-cells = <2>; 52 53 }; 54 55 UIC1: interrupt-controller1 { 56 compatible = "ibm,uic-440gp", "ibm,uic"; 57 interrupt-controller; 58 cell-index = <1>; 59 dcr-reg = <0d0 009>; 60 #address-cells = <0>; 61 #size-cells = <0>; 62 #interrupt-cells = <2>; 63 interrupts = <1e 4 1f 4>; /* cascade */ 64 interrupt-parent = <&UIC0>; 65 }; 66 67 CPC0: cpc { 68 compatible = "ibm,cpc-440gp"; 69 dcr-reg = <0b0 003 0e0 010>; 70 // FIXME: anything else? 71 }; 72 73 plb { 74 compatible = "ibm,plb-440gp", "ibm,plb4"; 75 #address-cells = <2>; 76 #size-cells = <1>; 77 ranges; 78 clock-frequency = <0>; // Filled in by zImage 79 80 SDRAM0: memory-controller { 81 compatible = "ibm,sdram-440gp"; 82 dcr-reg = <010 2>; 83 // FIXME: anything else? 84 }; 85 86 SRAM0: sram { 87 compatible = "ibm,sram-440gp"; 88 dcr-reg = <020 8 00a 1>; 89 }; 90 91 DMA0: dma { 92 // FIXME: ??? 93 compatible = "ibm,dma-440gp"; 94 dcr-reg = <100 027>; 95 }; 96 97 MAL0: mcmal { 98 compatible = "ibm,mcmal-440gp", "ibm,mcmal"; 99 dcr-reg = <180 62>; 100 num-tx-chans = <4>; 101 num-rx-chans = <4>; 102 interrupt-parent = <&MAL0>; 103 interrupts = <0 1 2 3 4>; 104 #interrupt-cells = <1>; 105 #address-cells = <0>; 106 #size-cells = <0>; 107 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 108 /*RXEOB*/ 1 &UIC0 b 4 109 /*SERR*/ 2 &UIC1 0 4 110 /*TXDE*/ 3 &UIC1 1 4 111 /*RXDE*/ 4 &UIC1 2 4>; 112 interrupt-map-mask = <ffffffff>; 113 }; 114 115 POB0: opb { 116 compatible = "ibm,opb-440gp", "ibm,opb"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 /* Wish there was a nicer way of specifying a full 32-bit 120 range */ 121 ranges = <00000000 1 00000000 80000000 122 80000000 1 80000000 80000000>; 123 dcr-reg = <090 00b>; 124 interrupt-parent = <&UIC1>; 125 interrupts = <7 4>; 126 clock-frequency = <0>; // Filled in by zImage 127 128 EBC0: ebc { 129 compatible = "ibm,ebc-440gp", "ibm,ebc"; 130 dcr-reg = <012 2>; 131 #address-cells = <2>; 132 #size-cells = <1>; 133 clock-frequency = <0>; // Filled in by zImage 134 // ranges property is supplied by zImage 135 // based on firmware's configuration of the 136 // EBC bridge 137 interrupts = <5 4>; 138 interrupt-parent = <&UIC1>; 139 140 small-flash@0,80000 { 141 compatible = "jedec-flash"; 142 bank-width = <1>; 143 reg = <0 80000 80000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 partition@0 { 147 label = "OpenBIOS"; 148 reg = <0 80000>; 149 read-only; 150 }; 151 }; 152 153 ds1743@1,0 { 154 /* NVRAM & RTC */ 155 compatible = "ds1743"; 156 reg = <1 0 2000>; 157 }; 158 159 large-flash@2,0 { 160 compatible = "jedec-flash"; 161 bank-width = <1>; 162 reg = <2 0 400000>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 partition@0 { 166 label = "fs"; 167 reg = <0 380000>; 168 }; 169 partition@380000 { 170 label = "firmware"; 171 reg = <380000 80000>; 172 }; 173 }; 174 175 ir@3,0 { 176 reg = <3 0 10>; 177 }; 178 179 fpga@7,0 { 180 compatible = "Ebony-FPGA"; 181 reg = <7 0 10>; 182 virtual-reg = <e8300000>; 183 }; 184 }; 185 186 UART0: serial@40000200 { 187 device_type = "serial"; 188 compatible = "ns16550"; 189 reg = <40000200 8>; 190 virtual-reg = <e0000200>; 191 clock-frequency = <A8C000>; 192 current-speed = <2580>; 193 interrupt-parent = <&UIC0>; 194 interrupts = <0 4>; 195 }; 196 197 UART1: serial@40000300 { 198 device_type = "serial"; 199 compatible = "ns16550"; 200 reg = <40000300 8>; 201 virtual-reg = <e0000300>; 202 clock-frequency = <A8C000>; 203 current-speed = <2580>; 204 interrupt-parent = <&UIC0>; 205 interrupts = <1 4>; 206 }; 207 208 IIC0: i2c@40000400 { 209 /* FIXME */ 210 device_type = "i2c"; 211 compatible = "ibm,iic-440gp", "ibm,iic"; 212 reg = <40000400 14>; 213 interrupt-parent = <&UIC0>; 214 interrupts = <2 4>; 215 }; 216 IIC1: i2c@40000500 { 217 /* FIXME */ 218 device_type = "i2c"; 219 compatible = "ibm,iic-440gp", "ibm,iic"; 220 reg = <40000500 14>; 221 interrupt-parent = <&UIC0>; 222 interrupts = <3 4>; 223 }; 224 225 GPIO0: gpio@40000700 { 226 /* FIXME */ 227 compatible = "ibm,gpio-440gp"; 228 reg = <40000700 20>; 229 }; 230 231 ZMII0: emac-zmii@40000780 { 232 compatible = "ibm,zmii-440gp", "ibm,zmii"; 233 reg = <40000780 c>; 234 }; 235 236 EMAC0: ethernet@40000800 { 237 linux,network-index = <0>; 238 device_type = "network"; 239 compatible = "ibm,emac-440gp", "ibm,emac"; 240 interrupt-parent = <&UIC1>; 241 interrupts = <1c 4 1d 4>; 242 reg = <40000800 70>; 243 local-mac-address = [000000000000]; // Filled in by zImage 244 mal-device = <&MAL0>; 245 mal-tx-channel = <0 1>; 246 mal-rx-channel = <0>; 247 cell-index = <0>; 248 max-frame-size = <5dc>; 249 rx-fifo-size = <1000>; 250 tx-fifo-size = <800>; 251 phy-mode = "rmii"; 252 phy-map = <00000001>; 253 zmii-device = <&ZMII0>; 254 zmii-channel = <0>; 255 }; 256 EMAC1: ethernet@40000900 { 257 linux,network-index = <1>; 258 device_type = "network"; 259 compatible = "ibm,emac-440gp", "ibm,emac"; 260 interrupt-parent = <&UIC1>; 261 interrupts = <1e 4 1f 4>; 262 reg = <40000900 70>; 263 local-mac-address = [000000000000]; // Filled in by zImage 264 mal-device = <&MAL0>; 265 mal-tx-channel = <2 3>; 266 mal-rx-channel = <1>; 267 cell-index = <1>; 268 max-frame-size = <5dc>; 269 rx-fifo-size = <1000>; 270 tx-fifo-size = <800>; 271 phy-mode = "rmii"; 272 phy-map = <00000001>; 273 zmii-device = <&ZMII0>; 274 zmii-channel = <1>; 275 }; 276 277 278 GPT0: gpt@40000a00 { 279 /* FIXME */ 280 reg = <40000a00 d4>; 281 interrupt-parent = <&UIC0>; 282 interrupts = <12 4 13 4 14 4 15 4 16 4>; 283 }; 284 285 }; 286 287 PCIX0: pci@20ec00000 { 288 device_type = "pci"; 289 #interrupt-cells = <1>; 290 #size-cells = <2>; 291 #address-cells = <3>; 292 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 293 primary; 294 reg = <2 0ec00000 8 /* Config space access */ 295 0 0 0 /* no IACK cycles */ 296 2 0ed00000 4 /* Special cycles */ 297 2 0ec80000 f0 /* Internal registers */ 298 2 0ec80100 fc>; /* Internal messaging registers */ 299 300 /* Outbound ranges, one memory and one IO, 301 * later cannot be changed 302 */ 303 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 304 01000000 0 00000000 00000002 08000000 0 00010000>; 305 306 /* Inbound 2GB range starting at 0 */ 307 dma-ranges = <42000000 0 0 0 0 0 80000000>; 308 309 /* Ebony has all 4 IRQ pins tied together per slot */ 310 interrupt-map-mask = <f800 0 0 0>; 311 interrupt-map = < 312 /* IDSEL 1 */ 313 0800 0 0 0 &UIC0 17 8 314 315 /* IDSEL 2 */ 316 1000 0 0 0 &UIC0 18 8 317 318 /* IDSEL 3 */ 319 1800 0 0 0 &UIC0 19 8 320 321 /* IDSEL 4 */ 322 2000 0 0 0 &UIC0 1a 8 323 >; 324 }; 325 }; 326 327 chosen { 328 linux,stdout-path = "/plb/opb/serial@40000200"; 329 }; 330}; 331