1/*
2 * Digsy MTC board Device Tree Source
3 *
4 * Copyright (C) 2009 Semihalf
5 *
6 * Based on the CM5200 by M. Balakowicz
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14/include/ "mpc5200b.dtsi"
15
16/ {
17	model = "intercontrol,digsy-mtc";
18	compatible = "intercontrol,digsy-mtc";
19
20	memory {
21		reg = <0x00000000 0x02000000>;	// 32MB
22	};
23
24	soc5200@f0000000 {
25		timer@600 {	// General Purpose Timer
26			fsl,has-wdt;
27		};
28
29		rtc@800 {
30			status = "disabled";
31		};
32
33		can@900 {
34			status = "disabled";
35		};
36
37		can@980 {
38			status = "disabled";
39		};
40
41		spi@f00 {
42			msp430@0 {
43				compatible = "spidev";
44				spi-max-frequency = <32000>;
45				reg = <0>;
46			};
47		};
48
49		psc@2000 {		// PSC1
50			status = "disabled";
51		};
52
53		psc@2200 {		// PSC2
54			status = "disabled";
55		};
56
57		psc@2400 {		// PSC3
58			status = "disabled";
59		};
60
61		psc@2600 {		// PSC4
62			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
63		};
64
65		psc@2800 {		// PSC5
66			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
67		};
68
69		psc@2c00 {		// PSC6
70			status = "disabled";
71		};
72
73		ethernet@3000 {
74			phy-handle = <&phy0>;
75		};
76
77		mdio@3000 {
78			phy0: ethernet-phy@0 {
79				reg = <0>;
80			};
81		};
82
83		i2c@3d00 {
84			eeprom@50 {
85				compatible = "at,24c08";
86				reg = <0x50>;
87			};
88
89			rtc@56 {
90				compatible = "mc,rv3029c2";
91				reg = <0x56>;
92			};
93
94			rtc@68 {
95				compatible = "dallas,ds1339";
96				reg = <0x68>;
97			};
98		};
99
100		i2c@3d40 {
101			status = "disabled";
102		};
103	};
104
105	pci@f0000d00 {
106		interrupt-map-mask = <0xf800 0 0 7>;
107		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
108				 0xc000 0 0 2 &mpc5200_pic 0 0 3
109				 0xc000 0 0 3 &mpc5200_pic 0 0 3
110				 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
111		clock-frequency = <0>; // From boot loader
112		interrupts = <2 8 0 2 9 0 2 10 0>;
113		bus-range = <0 0>;
114		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
115			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
116			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
117	};
118
119	localbus {
120		ranges = <0 0 0xff000000 0x1000000
121			  4 0 0x60000000 0x0001000>;
122
123		// 16-bit flash device at LocalPlus Bus CS0
124		flash@0,0 {
125			compatible = "cfi-flash";
126			reg = <0 0 0x1000000>;
127			bank-width = <2>;
128			device-width = <2>;
129			#size-cells = <1>;
130			#address-cells = <1>;
131
132			partition@0 {
133				label = "kernel";
134				reg = <0x0 0x00200000>;
135			};
136			partition@200000 {
137				label = "root";
138				reg = <0x00200000 0x00300000>;
139			};
140			partition@500000 {
141				label = "user";
142				reg = <0x00500000 0x00a00000>;
143			};
144			partition@f00000 {
145				label = "u-boot";
146				reg = <0x00f00000 0x100000>;
147			};
148		};
149
150		can@4,0 {
151			compatible = "nxp,sja1000";
152			reg = <4 0x000 0x80>;
153			nxp,external-clock-frequency = <24000000>;
154			interrupts = <1 2 3>; // Level-low
155		};
156
157		can@4,100 {
158			compatible = "nxp,sja1000";
159			reg = <4 0x100 0x80>;
160			nxp,external-clock-frequency = <24000000>;
161			interrupts = <1 2 3>;  // Level-low
162		};
163
164		serial@4,200 {
165			compatible = "nxp,sc28l92";
166			reg = <4 0x200 0x10>;
167			interrupts = <1 3 3>;
168		};
169	};
170};
171