1/* 2 * Digsy MTC board Device Tree Source 3 * 4 * Copyright (C) 2009 Semihalf 5 * 6 * Based on the CM5200 by M. Balakowicz 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14/include/ "mpc5200b.dtsi" 15 16/ { 17 model = "intercontrol,digsy-mtc"; 18 compatible = "intercontrol,digsy-mtc"; 19 20 memory { 21 reg = <0x00000000 0x02000000>; // 32MB 22 }; 23 24 soc5200@f0000000 { 25 timer@600 { // General Purpose Timer 26 #gpio-cells = <2>; 27 fsl,has-wdt; 28 gpio-controller; 29 }; 30 31 timer@610 { 32 #gpio-cells = <2>; 33 gpio-controller; 34 }; 35 36 rtc@800 { 37 status = "disabled"; 38 }; 39 40 can@900 { 41 status = "disabled"; 42 }; 43 44 can@980 { 45 status = "disabled"; 46 }; 47 48 spi@f00 { 49 msp430@0 { 50 compatible = "spidev"; 51 spi-max-frequency = <32000>; 52 reg = <0>; 53 }; 54 }; 55 56 psc@2000 { // PSC1 57 status = "disabled"; 58 }; 59 60 psc@2200 { // PSC2 61 status = "disabled"; 62 }; 63 64 psc@2400 { // PSC3 65 status = "disabled"; 66 }; 67 68 psc@2600 { // PSC4 69 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 70 }; 71 72 psc@2800 { // PSC5 73 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 74 }; 75 76 psc@2c00 { // PSC6 77 status = "disabled"; 78 }; 79 80 ethernet@3000 { 81 phy-handle = <&phy0>; 82 }; 83 84 mdio@3000 { 85 phy0: ethernet-phy@0 { 86 reg = <0>; 87 }; 88 }; 89 90 i2c@3d00 { 91 eeprom@50 { 92 compatible = "at,24c08"; 93 reg = <0x50>; 94 }; 95 96 rtc@56 { 97 compatible = "mc,rv3029c2"; 98 reg = <0x56>; 99 }; 100 101 rtc@68 { 102 compatible = "dallas,ds1339"; 103 reg = <0x68>; 104 }; 105 }; 106 107 i2c@3d40 { 108 status = "disabled"; 109 }; 110 }; 111 112 pci@f0000d00 { 113 interrupt-map-mask = <0xf800 0 0 7>; 114 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 115 0xc000 0 0 2 &mpc5200_pic 0 0 3 116 0xc000 0 0 3 &mpc5200_pic 0 0 3 117 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 118 clock-frequency = <0>; // From boot loader 119 interrupts = <2 8 0 2 9 0 2 10 0>; 120 bus-range = <0 0>; 121 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 122 0x02000000 0 0x90000000 0x90000000 0 0x10000000 123 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 124 }; 125 126 localbus { 127 ranges = <0 0 0xff000000 0x1000000 128 4 0 0x60000000 0x0001000>; 129 130 // 16-bit flash device at LocalPlus Bus CS0 131 flash@0,0 { 132 compatible = "cfi-flash"; 133 reg = <0 0 0x1000000>; 134 bank-width = <2>; 135 device-width = <2>; 136 #size-cells = <1>; 137 #address-cells = <1>; 138 139 partition@0 { 140 label = "kernel"; 141 reg = <0x0 0x00200000>; 142 }; 143 partition@200000 { 144 label = "root"; 145 reg = <0x00200000 0x00300000>; 146 }; 147 partition@500000 { 148 label = "user"; 149 reg = <0x00500000 0x00a00000>; 150 }; 151 partition@f00000 { 152 label = "u-boot"; 153 reg = <0x00f00000 0x100000>; 154 }; 155 }; 156 157 can@4,0 { 158 compatible = "nxp,sja1000"; 159 reg = <4 0x000 0x80>; 160 nxp,external-clock-frequency = <24000000>; 161 interrupts = <1 2 3>; // Level-low 162 }; 163 164 can@4,100 { 165 compatible = "nxp,sja1000"; 166 reg = <4 0x100 0x80>; 167 nxp,external-clock-frequency = <24000000>; 168 interrupts = <1 2 3>; // Level-low 169 }; 170 171 serial@4,200 { 172 compatible = "nxp,sc28l92"; 173 reg = <4 0x200 0x10>; 174 interrupts = <1 3 3>; 175 }; 176 }; 177}; 178