1/* 2 * CM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/* 14 * WARNING: Do not depend on this tree layout remaining static just yet. 15 * The MPC5200 device tree conventions are still in flux 16 * Keep an eye on the linuxppc-dev mailing list for more details 17 */ 18 19/ { 20 model = "schindler,cm5200"; 21 compatible = "schindler,cm5200"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,5200@0 { 30 device_type = "cpu"; 31 reg = <0>; 32 d-cache-line-size = <20>; 33 i-cache-line-size = <20>; 34 d-cache-size = <4000>; // L1, 16K 35 i-cache-size = <4000>; // L1, 16K 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 39 }; 40 }; 41 42 memory { 43 device_type = "memory"; 44 reg = <00000000 04000000>; // 64MB 45 }; 46 47 soc5200@f0000000 { 48 model = "fsl,mpc5200b"; 49 compatible = "fsl,mpc5200b"; 50 revision = ""; // from bootloader 51 device_type = "soc"; 52 ranges = <0 f0000000 0000c000>; 53 reg = <f0000000 00000100>; 54 bus-frequency = <0>; // from bootloader 55 system-frequency = <0>; // from bootloader 56 57 cdm@200 { 58 compatible = "mpc5200b-cdm","mpc5200-cdm"; 59 reg = <200 38>; 60 }; 61 62 mpc5200_pic: pic@500 { 63 // 5200 interrupts are encoded into two levels; 64 interrupt-controller; 65 #interrupt-cells = <3>; 66 compatible = "mpc5200b-pic","mpc5200-pic"; 67 reg = <500 80>; 68 }; 69 70 gpt@600 { // General Purpose Timer 71 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 72 reg = <600 10>; 73 interrupts = <1 9 0>; 74 interrupt-parent = <&mpc5200_pic>; 75 fsl,has-wdt; 76 }; 77 78 gpt@610 { // General Purpose Timer 79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 reg = <610 10>; 81 interrupts = <1 a 0>; 82 interrupt-parent = <&mpc5200_pic>; 83 }; 84 85 gpt@620 { // General Purpose Timer 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 87 reg = <620 10>; 88 interrupts = <1 b 0>; 89 interrupt-parent = <&mpc5200_pic>; 90 }; 91 92 gpt@630 { // General Purpose Timer 93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 94 reg = <630 10>; 95 interrupts = <1 c 0>; 96 interrupt-parent = <&mpc5200_pic>; 97 }; 98 99 gpt@640 { // General Purpose Timer 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 101 reg = <640 10>; 102 interrupts = <1 d 0>; 103 interrupt-parent = <&mpc5200_pic>; 104 }; 105 106 gpt@650 { // General Purpose Timer 107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 108 reg = <650 10>; 109 interrupts = <1 e 0>; 110 interrupt-parent = <&mpc5200_pic>; 111 }; 112 113 gpt@660 { // General Purpose Timer 114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 115 reg = <660 10>; 116 interrupts = <1 f 0>; 117 interrupt-parent = <&mpc5200_pic>; 118 }; 119 120 gpt@670 { // General Purpose Timer 121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 122 reg = <670 10>; 123 interrupts = <1 10 0>; 124 interrupt-parent = <&mpc5200_pic>; 125 }; 126 127 rtc@800 { // Real time clock 128 compatible = "mpc5200b-rtc","mpc5200-rtc"; 129 reg = <800 100>; 130 interrupts = <1 5 0 1 6 0>; 131 interrupt-parent = <&mpc5200_pic>; 132 }; 133 134 gpio@b00 { 135 compatible = "mpc5200b-gpio","mpc5200-gpio"; 136 reg = <b00 40>; 137 interrupts = <1 7 0>; 138 interrupt-parent = <&mpc5200_pic>; 139 }; 140 141 gpio-wkup@c00 { 142 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 143 reg = <c00 40>; 144 interrupts = <1 8 0 0 3 0>; 145 interrupt-parent = <&mpc5200_pic>; 146 }; 147 148 spi@f00 { 149 compatible = "mpc5200b-spi","mpc5200-spi"; 150 reg = <f00 20>; 151 interrupts = <2 d 0 2 e 0>; 152 interrupt-parent = <&mpc5200_pic>; 153 }; 154 155 usb@1000 { 156 device_type = "usb-ohci-be"; 157 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; 158 reg = <1000 ff>; 159 interrupts = <2 6 0>; 160 interrupt-parent = <&mpc5200_pic>; 161 }; 162 163 dma-controller@1200 { 164 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 165 reg = <1200 80>; 166 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 167 3 4 0 3 5 0 3 6 0 3 7 0 168 3 8 0 3 9 0 3 a 0 3 b 0 169 3 c 0 3 d 0 3 e 0 3 f 0>; 170 interrupt-parent = <&mpc5200_pic>; 171 }; 172 173 xlb@1f00 { 174 compatible = "mpc5200b-xlb","mpc5200-xlb"; 175 reg = <1f00 100>; 176 }; 177 178 serial@2000 { // PSC1 179 device_type = "serial"; 180 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 181 port-number = <0>; // Logical port assignment 182 reg = <2000 100>; 183 interrupts = <2 1 0>; 184 interrupt-parent = <&mpc5200_pic>; 185 }; 186 187 serial@2200 { // PSC2 188 device_type = "serial"; 189 compatible = "mpc5200-psc-uart"; 190 port-number = <1>; // Logical port assignment 191 reg = <2200 100>; 192 interrupts = <2 2 0>; 193 interrupt-parent = <&mpc5200_pic>; 194 }; 195 196 serial@2400 { // PSC3 197 device_type = "serial"; 198 compatible = "mpc5200-psc-uart"; 199 port-number = <2>; // Logical port assignment 200 reg = <2400 100>; 201 interrupts = <2 3 0>; 202 interrupt-parent = <&mpc5200_pic>; 203 }; 204 205 serial@2c00 { // PSC6 206 device_type = "serial"; 207 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 208 port-number = <5>; // Logical port assignment 209 reg = <2c00 100>; 210 interrupts = <2 4 0>; 211 interrupt-parent = <&mpc5200_pic>; 212 }; 213 214 ethernet@3000 { 215 device_type = "network"; 216 compatible = "mpc5200b-fec","mpc5200-fec"; 217 reg = <3000 800>; 218 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 219 interrupts = <2 5 0>; 220 interrupt-parent = <&mpc5200_pic>; 221 }; 222 223 i2c@3d40 { 224 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 225 reg = <3d40 40>; 226 interrupts = <2 10 0>; 227 interrupt-parent = <&mpc5200_pic>; 228 fsl5200-clocking; 229 }; 230 231 sram@8000 { 232 compatible = "mpc5200b-sram","mpc5200-sram"; 233 reg = <8000 4000>; 234 }; 235 }; 236}; 237