1/* 2 * CM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/* 14 * WARNING: Do not depend on this tree layout remaining static just yet. 15 * The MPC5200 device tree conventions are still in flux 16 * Keep an eye on the linuxppc-dev mailing list for more details 17 */ 18 19/ { 20 model = "schindler,cm5200"; 21 compatible = "schindler,cm5200"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,5200@0 { 30 device_type = "cpu"; 31 reg = <0>; 32 d-cache-line-size = <20>; 33 i-cache-line-size = <20>; 34 d-cache-size = <4000>; // L1, 16K 35 i-cache-size = <4000>; // L1, 16K 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 39 }; 40 }; 41 42 memory { 43 device_type = "memory"; 44 reg = <00000000 04000000>; // 64MB 45 }; 46 47 soc5200@f0000000 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 model = "fsl,mpc5200b"; 51 compatible = "fsl,mpc5200b"; 52 revision = ""; // from bootloader 53 device_type = "soc"; 54 ranges = <0 f0000000 0000c000>; 55 reg = <f0000000 00000100>; 56 bus-frequency = <0>; // from bootloader 57 system-frequency = <0>; // from bootloader 58 59 cdm@200 { 60 compatible = "mpc5200b-cdm","mpc5200-cdm"; 61 reg = <200 38>; 62 }; 63 64 mpc5200_pic: pic@500 { 65 // 5200 interrupts are encoded into two levels; 66 interrupt-controller; 67 #interrupt-cells = <3>; 68 compatible = "mpc5200b-pic","mpc5200-pic"; 69 reg = <500 80>; 70 }; 71 72 gpt@600 { // General Purpose Timer 73 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 reg = <600 10>; 75 interrupts = <1 9 0>; 76 interrupt-parent = <&mpc5200_pic>; 77 fsl,has-wdt; 78 }; 79 80 gpt@610 { // General Purpose Timer 81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 82 reg = <610 10>; 83 interrupts = <1 a 0>; 84 interrupt-parent = <&mpc5200_pic>; 85 }; 86 87 gpt@620 { // General Purpose Timer 88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 89 reg = <620 10>; 90 interrupts = <1 b 0>; 91 interrupt-parent = <&mpc5200_pic>; 92 }; 93 94 gpt@630 { // General Purpose Timer 95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 96 reg = <630 10>; 97 interrupts = <1 c 0>; 98 interrupt-parent = <&mpc5200_pic>; 99 }; 100 101 gpt@640 { // General Purpose Timer 102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 103 reg = <640 10>; 104 interrupts = <1 d 0>; 105 interrupt-parent = <&mpc5200_pic>; 106 }; 107 108 gpt@650 { // General Purpose Timer 109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 reg = <650 10>; 111 interrupts = <1 e 0>; 112 interrupt-parent = <&mpc5200_pic>; 113 }; 114 115 gpt@660 { // General Purpose Timer 116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 117 reg = <660 10>; 118 interrupts = <1 f 0>; 119 interrupt-parent = <&mpc5200_pic>; 120 }; 121 122 gpt@670 { // General Purpose Timer 123 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 124 reg = <670 10>; 125 interrupts = <1 10 0>; 126 interrupt-parent = <&mpc5200_pic>; 127 }; 128 129 rtc@800 { // Real time clock 130 compatible = "mpc5200b-rtc","mpc5200-rtc"; 131 reg = <800 100>; 132 interrupts = <1 5 0 1 6 0>; 133 interrupt-parent = <&mpc5200_pic>; 134 }; 135 136 gpio@b00 { 137 compatible = "mpc5200b-gpio","mpc5200-gpio"; 138 reg = <b00 40>; 139 interrupts = <1 7 0>; 140 interrupt-parent = <&mpc5200_pic>; 141 }; 142 143 gpio-wkup@c00 { 144 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 145 reg = <c00 40>; 146 interrupts = <1 8 0 0 3 0>; 147 interrupt-parent = <&mpc5200_pic>; 148 }; 149 150 spi@f00 { 151 compatible = "mpc5200b-spi","mpc5200-spi"; 152 reg = <f00 20>; 153 interrupts = <2 d 0 2 e 0>; 154 interrupt-parent = <&mpc5200_pic>; 155 }; 156 157 usb@1000 { 158 device_type = "usb-ohci-be"; 159 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; 160 reg = <1000 ff>; 161 interrupts = <2 6 0>; 162 interrupt-parent = <&mpc5200_pic>; 163 }; 164 165 dma-controller@1200 { 166 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 167 reg = <1200 80>; 168 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 169 3 4 0 3 5 0 3 6 0 3 7 0 170 3 8 0 3 9 0 3 a 0 3 b 0 171 3 c 0 3 d 0 3 e 0 3 f 0>; 172 interrupt-parent = <&mpc5200_pic>; 173 }; 174 175 xlb@1f00 { 176 compatible = "mpc5200b-xlb","mpc5200-xlb"; 177 reg = <1f00 100>; 178 }; 179 180 serial@2000 { // PSC1 181 device_type = "serial"; 182 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 183 port-number = <0>; // Logical port assignment 184 reg = <2000 100>; 185 interrupts = <2 1 0>; 186 interrupt-parent = <&mpc5200_pic>; 187 }; 188 189 serial@2200 { // PSC2 190 device_type = "serial"; 191 compatible = "mpc5200-psc-uart"; 192 port-number = <1>; // Logical port assignment 193 reg = <2200 100>; 194 interrupts = <2 2 0>; 195 interrupt-parent = <&mpc5200_pic>; 196 }; 197 198 serial@2400 { // PSC3 199 device_type = "serial"; 200 compatible = "mpc5200-psc-uart"; 201 port-number = <2>; // Logical port assignment 202 reg = <2400 100>; 203 interrupts = <2 3 0>; 204 interrupt-parent = <&mpc5200_pic>; 205 }; 206 207 serial@2c00 { // PSC6 208 device_type = "serial"; 209 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 210 port-number = <5>; // Logical port assignment 211 reg = <2c00 100>; 212 interrupts = <2 4 0>; 213 interrupt-parent = <&mpc5200_pic>; 214 }; 215 216 ethernet@3000 { 217 device_type = "network"; 218 compatible = "mpc5200b-fec","mpc5200-fec"; 219 reg = <3000 800>; 220 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 221 interrupts = <2 5 0>; 222 interrupt-parent = <&mpc5200_pic>; 223 }; 224 225 i2c@3d40 { 226 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 227 reg = <3d40 40>; 228 interrupts = <2 10 0>; 229 interrupt-parent = <&mpc5200_pic>; 230 fsl5200-clocking; 231 }; 232 233 sram@8000 { 234 compatible = "mpc5200b-sram","mpc5200-sram"; 235 reg = <8000 4000>; 236 }; 237 }; 238}; 239