1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2.  This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <1>;
16	model = "amcc,canyonlands";
17	compatible = "amcc,canyonlands";
18	dcr-parent = <&{/cpus/cpu@0}>;
19
20	aliases {
21		ethernet0 = &EMAC0;
22		ethernet1 = &EMAC1;
23		serial0 = &UART0;
24		serial1 = &UART1;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu@0 {
32			device_type = "cpu";
33			model = "PowerPC,460EX";
34			reg = <0x00000000>;
35			clock-frequency = <0>; /* Filled in by U-Boot */
36			timebase-frequency = <0>; /* Filled in by U-Boot */
37			i-cache-line-size = <32>;
38			d-cache-line-size = <32>;
39			i-cache-size = <32768>;
40			d-cache-size = <32768>;
41			dcr-controller;
42			dcr-access-method = "native";
43			next-level-cache = <&L2C0>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
50	};
51
52	UIC0: interrupt-controller0 {
53		compatible = "ibm,uic-460ex","ibm,uic";
54		interrupt-controller;
55		cell-index = <0>;
56		dcr-reg = <0x0c0 0x009>;
57		#address-cells = <0>;
58		#size-cells = <0>;
59		#interrupt-cells = <2>;
60	};
61
62	UIC1: interrupt-controller1 {
63		compatible = "ibm,uic-460ex","ibm,uic";
64		interrupt-controller;
65		cell-index = <1>;
66		dcr-reg = <0x0d0 0x009>;
67		#address-cells = <0>;
68		#size-cells = <0>;
69		#interrupt-cells = <2>;
70		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71		interrupt-parent = <&UIC0>;
72	};
73
74	UIC2: interrupt-controller2 {
75		compatible = "ibm,uic-460ex","ibm,uic";
76		interrupt-controller;
77		cell-index = <2>;
78		dcr-reg = <0x0e0 0x009>;
79		#address-cells = <0>;
80		#size-cells = <0>;
81		#interrupt-cells = <2>;
82		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83		interrupt-parent = <&UIC0>;
84	};
85
86	UIC3: interrupt-controller3 {
87		compatible = "ibm,uic-460ex","ibm,uic";
88		interrupt-controller;
89		cell-index = <3>;
90		dcr-reg = <0x0f0 0x009>;
91		#address-cells = <0>;
92		#size-cells = <0>;
93		#interrupt-cells = <2>;
94		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95		interrupt-parent = <&UIC0>;
96	};
97
98	SDR0: sdr {
99		compatible = "ibm,sdr-460ex";
100		dcr-reg = <0x00e 0x002>;
101	};
102
103	CPR0: cpr {
104		compatible = "ibm,cpr-460ex";
105		dcr-reg = <0x00c 0x002>;
106	};
107
108	CPM0: cpm {
109		compatible = "ibm,cpm";
110		dcr-access-method = "native";
111		dcr-reg = <0x160 0x003>;
112		unused-units = <0x00000100>;
113		idle-doze = <0x02000000>;
114		standby = <0xfeff791d>;
115	};
116
117	L2C0: l2c {
118		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
120			   0x030 0x008>;	/* L2 cache DCR's */
121		cache-line-size = <32>;		/* 32 bytes */
122		cache-size = <262144>;		/* L2, 256K */
123		interrupt-parent = <&UIC1>;
124		interrupts = <11 1>;
125	};
126
127	plb {
128		compatible = "ibm,plb-460ex", "ibm,plb4";
129		#address-cells = <2>;
130		#size-cells = <1>;
131		ranges;
132		clock-frequency = <0>; /* Filled in by U-Boot */
133
134		SDRAM0: sdram {
135			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
136			dcr-reg = <0x010 0x002>;
137		};
138
139		CRYPTO: crypto@180000 {
140			compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
141			reg = <4 0x00180000 0x80400>;
142			interrupt-parent = <&UIC0>;
143			interrupts = <0x1d 0x4>;
144		};
145
146		MAL0: mcmal {
147			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
148			dcr-reg = <0x180 0x062>;
149			num-tx-chans = <2>;
150			num-rx-chans = <16>;
151			#address-cells = <0>;
152			#size-cells = <0>;
153			interrupt-parent = <&UIC2>;
154			interrupts = <	/*TXEOB*/ 0x6 0x4
155					/*RXEOB*/ 0x7 0x4
156					/*SERR*/  0x3 0x4
157					/*TXDE*/  0x4 0x4
158					/*RXDE*/  0x5 0x4>;
159		};
160
161		USB0: ehci@bffd0400 {
162			compatible = "ibm,usb-ehci-460ex", "usb-ehci";
163			interrupt-parent = <&UIC2>;
164			interrupts = <0x1d 4>;
165			reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
166		};
167
168		USB1: usb@bffd0000 {
169			compatible = "ohci-le";
170			reg = <4 0xbffd0000 0x60>;
171			interrupt-parent = <&UIC2>;
172			interrupts = <0x1e 4>;
173		};
174
175		SATA0: sata@bffd1000 {
176			compatible = "amcc,sata-460ex";
177			reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
178			interrupt-parent = <&UIC3>;
179			interrupts = <0x0 0x4       /* SATA */
180				      0x5 0x4>;     /* AHBDMA */
181		};
182
183		POB0: opb {
184			compatible = "ibm,opb-460ex", "ibm,opb";
185			#address-cells = <1>;
186			#size-cells = <1>;
187			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
188			clock-frequency = <0>; /* Filled in by U-Boot */
189
190			EBC0: ebc {
191				compatible = "ibm,ebc-460ex", "ibm,ebc";
192				dcr-reg = <0x012 0x002>;
193				#address-cells = <2>;
194				#size-cells = <1>;
195				clock-frequency = <0>; /* Filled in by U-Boot */
196				/* ranges property is supplied by U-Boot */
197				interrupts = <0x6 0x4>;
198				interrupt-parent = <&UIC1>;
199
200				nor_flash@0,0 {
201					compatible = "amd,s29gl512n", "cfi-flash";
202					bank-width = <2>;
203					reg = <0x00000000 0x00000000 0x04000000>;
204					#address-cells = <1>;
205					#size-cells = <1>;
206					partition@0 {
207						label = "kernel";
208						reg = <0x00000000 0x001e0000>;
209					};
210					partition@1e0000 {
211						label = "dtb";
212						reg = <0x001e0000 0x00020000>;
213					};
214					partition@200000 {
215						label = "ramdisk";
216						reg = <0x00200000 0x01400000>;
217					};
218					partition@1600000 {
219						label = "jffs2";
220						reg = <0x01600000 0x00400000>;
221					};
222					partition@1a00000 {
223						label = "user";
224						reg = <0x01a00000 0x02560000>;
225					};
226					partition@3f60000 {
227						label = "env";
228						reg = <0x03f60000 0x00040000>;
229					};
230					partition@3fa0000 {
231						label = "u-boot";
232						reg = <0x03fa0000 0x00060000>;
233					};
234				};
235
236				ndfc@3,0 {
237					compatible = "ibm,ndfc";
238					reg = <0x00000003 0x00000000 0x00002000>;
239					ccr = <0x00001000>;
240					bank-settings = <0x80002222>;
241					#address-cells = <1>;
242					#size-cells = <1>;
243
244					nand {
245						#address-cells = <1>;
246						#size-cells = <1>;
247
248						partition@0 {
249							label = "u-boot";
250							reg = <0x00000000 0x00100000>;
251						};
252						partition@100000 {
253							label = "user";
254							reg = <0x00000000 0x03f00000>;
255						};
256					};
257				};
258			};
259
260			UART0: serial@ef600300 {
261				device_type = "serial";
262				compatible = "ns16550";
263				reg = <0xef600300 0x00000008>;
264				virtual-reg = <0xef600300>;
265				clock-frequency = <0>; /* Filled in by U-Boot */
266				current-speed = <0>; /* Filled in by U-Boot */
267				interrupt-parent = <&UIC1>;
268				interrupts = <0x1 0x4>;
269			};
270
271			UART1: serial@ef600400 {
272				device_type = "serial";
273				compatible = "ns16550";
274				reg = <0xef600400 0x00000008>;
275				virtual-reg = <0xef600400>;
276				clock-frequency = <0>; /* Filled in by U-Boot */
277				current-speed = <0>; /* Filled in by U-Boot */
278				interrupt-parent = <&UIC0>;
279				interrupts = <0x1 0x4>;
280			};
281
282			IIC0: i2c@ef600700 {
283				compatible = "ibm,iic-460ex", "ibm,iic";
284				reg = <0xef600700 0x00000014>;
285				interrupt-parent = <&UIC0>;
286				interrupts = <0x2 0x4>;
287				#address-cells = <1>;
288				#size-cells = <0>;
289                                rtc@68 {
290                                        compatible = "stm,m41t80";
291                                        reg = <0x68>;
292					interrupt-parent = <&UIC2>;
293					interrupts = <0x19 0x8>;
294                                };
295                                sttm@48 {
296                                        compatible = "ad,ad7414";
297                                        reg = <0x48>;
298					interrupt-parent = <&UIC1>;
299					interrupts = <0x14 0x8>;
300                                };
301			};
302
303			IIC1: i2c@ef600800 {
304				compatible = "ibm,iic-460ex", "ibm,iic";
305				reg = <0xef600800 0x00000014>;
306				interrupt-parent = <&UIC0>;
307				interrupts = <0x3 0x4>;
308			};
309
310			ZMII0: emac-zmii@ef600d00 {
311				compatible = "ibm,zmii-460ex", "ibm,zmii";
312				reg = <0xef600d00 0x0000000c>;
313			};
314
315			RGMII0: emac-rgmii@ef601500 {
316				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
317				reg = <0xef601500 0x00000008>;
318				has-mdio;
319			};
320
321			TAH0: emac-tah@ef601350 {
322				compatible = "ibm,tah-460ex", "ibm,tah";
323				reg = <0xef601350 0x00000030>;
324			};
325
326			TAH1: emac-tah@ef601450 {
327				compatible = "ibm,tah-460ex", "ibm,tah";
328				reg = <0xef601450 0x00000030>;
329			};
330
331			EMAC0: ethernet@ef600e00 {
332				device_type = "network";
333				compatible = "ibm,emac-460ex", "ibm,emac4sync";
334				interrupt-parent = <&EMAC0>;
335				interrupts = <0x0 0x1>;
336				#interrupt-cells = <1>;
337				#address-cells = <0>;
338				#size-cells = <0>;
339				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
340						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
341				reg = <0xef600e00 0x000000c4>;
342				local-mac-address = [000000000000]; /* Filled in by U-Boot */
343				mal-device = <&MAL0>;
344				mal-tx-channel = <0>;
345				mal-rx-channel = <0>;
346				cell-index = <0>;
347				max-frame-size = <9000>;
348				rx-fifo-size = <4096>;
349				tx-fifo-size = <2048>;
350				rx-fifo-size-gige = <16384>;
351				phy-mode = "rgmii";
352				phy-map = <0x00000000>;
353				rgmii-device = <&RGMII0>;
354				rgmii-channel = <0>;
355				tah-device = <&TAH0>;
356				tah-channel = <0>;
357				has-inverted-stacr-oc;
358				has-new-stacr-staopc;
359			};
360
361			EMAC1: ethernet@ef600f00 {
362				device_type = "network";
363				compatible = "ibm,emac-460ex", "ibm,emac4sync";
364				interrupt-parent = <&EMAC1>;
365				interrupts = <0x0 0x1>;
366				#interrupt-cells = <1>;
367				#address-cells = <0>;
368				#size-cells = <0>;
369				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
370						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
371				reg = <0xef600f00 0x000000c4>;
372				local-mac-address = [000000000000]; /* Filled in by U-Boot */
373				mal-device = <&MAL0>;
374				mal-tx-channel = <1>;
375				mal-rx-channel = <8>;
376				cell-index = <1>;
377				max-frame-size = <9000>;
378				rx-fifo-size = <4096>;
379				tx-fifo-size = <2048>;
380				rx-fifo-size-gige = <16384>;
381				phy-mode = "rgmii";
382				phy-map = <0x00000000>;
383				rgmii-device = <&RGMII0>;
384				rgmii-channel = <1>;
385				tah-device = <&TAH1>;
386				tah-channel = <1>;
387				has-inverted-stacr-oc;
388				has-new-stacr-staopc;
389				mdio-device = <&EMAC0>;
390			};
391		};
392
393		PCIX0: pci@c0ec00000 {
394			device_type = "pci";
395			#interrupt-cells = <1>;
396			#size-cells = <2>;
397			#address-cells = <3>;
398			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
399			primary;
400			large-inbound-windows;
401			enable-msi-hole;
402			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
403			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
404			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
405			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
406			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */
407
408			/* Outbound ranges, one memory and one IO,
409			 * later cannot be changed
410			 */
411			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
412				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
413				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
414
415			/* Inbound 2GB range starting at 0 */
416			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
417
418			/* This drives busses 0 to 0x3f */
419			bus-range = <0x0 0x3f>;
420
421			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
422			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
423			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
424		};
425
426		PCIE0: pciex@d00000000 {
427			device_type = "pci";
428			#interrupt-cells = <1>;
429			#size-cells = <2>;
430			#address-cells = <3>;
431			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
432			primary;
433			port = <0x0>; /* port number */
434			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
435			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
436			dcr-reg = <0x100 0x020>;
437			sdr-base = <0x300>;
438
439			/* Outbound ranges, one memory and one IO,
440			 * later cannot be changed
441			 */
442			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
443				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
444				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
445
446			/* Inbound 2GB range starting at 0 */
447			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
448
449			/* This drives busses 40 to 0x7f */
450			bus-range = <0x40 0x7f>;
451
452			/* Legacy interrupts (note the weird polarity, the bridge seems
453			 * to invert PCIe legacy interrupts).
454			 * We are de-swizzling here because the numbers are actually for
455			 * port of the root complex virtual P2P bridge. But I want
456			 * to avoid putting a node for it in the tree, so the numbers
457			 * below are basically de-swizzled numbers.
458			 * The real slot is on idsel 0, so the swizzling is 1:1
459			 */
460			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
461			interrupt-map = <
462				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
463				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
464				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
465				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
466		};
467
468		PCIE1: pciex@d20000000 {
469			device_type = "pci";
470			#interrupt-cells = <1>;
471			#size-cells = <2>;
472			#address-cells = <3>;
473			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
474			primary;
475			port = <0x1>; /* port number */
476			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
477			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
478			dcr-reg = <0x120 0x020>;
479			sdr-base = <0x340>;
480
481			/* Outbound ranges, one memory and one IO,
482			 * later cannot be changed
483			 */
484			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
485				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
486				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
487
488			/* Inbound 2GB range starting at 0 */
489			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
490
491			/* This drives busses 80 to 0xbf */
492			bus-range = <0x80 0xbf>;
493
494			/* Legacy interrupts (note the weird polarity, the bridge seems
495			 * to invert PCIe legacy interrupts).
496			 * We are de-swizzling here because the numbers are actually for
497			 * port of the root complex virtual P2P bridge. But I want
498			 * to avoid putting a node for it in the tree, so the numbers
499			 * below are basically de-swizzled numbers.
500			 * The real slot is on idsel 0, so the swizzling is 1:1
501			 */
502			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
503			interrupt-map = <
504				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
505				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
506				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
507				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
508		};
509	};
510};
511