1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2.  This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <1>;
16	model = "amcc,canyonlands";
17	compatible = "amcc,canyonlands";
18	dcr-parent = <&{/cpus/cpu@0}>;
19
20	aliases {
21		ethernet0 = &EMAC0;
22		ethernet1 = &EMAC1;
23		serial0 = &UART0;
24		serial1 = &UART1;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu@0 {
32			device_type = "cpu";
33			model = "PowerPC,460EX";
34			reg = <0x00000000>;
35			clock-frequency = <0>; /* Filled in by U-Boot */
36			timebase-frequency = <0>; /* Filled in by U-Boot */
37			i-cache-line-size = <32>;
38			d-cache-line-size = <32>;
39			i-cache-size = <32768>;
40			d-cache-size = <32768>;
41			dcr-controller;
42			dcr-access-method = "native";
43			next-level-cache = <&L2C0>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
50	};
51
52	UIC0: interrupt-controller0 {
53		compatible = "ibm,uic-460ex","ibm,uic";
54		interrupt-controller;
55		cell-index = <0>;
56		dcr-reg = <0x0c0 0x009>;
57		#address-cells = <0>;
58		#size-cells = <0>;
59		#interrupt-cells = <2>;
60	};
61
62	UIC1: interrupt-controller1 {
63		compatible = "ibm,uic-460ex","ibm,uic";
64		interrupt-controller;
65		cell-index = <1>;
66		dcr-reg = <0x0d0 0x009>;
67		#address-cells = <0>;
68		#size-cells = <0>;
69		#interrupt-cells = <2>;
70		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71		interrupt-parent = <&UIC0>;
72	};
73
74	UIC2: interrupt-controller2 {
75		compatible = "ibm,uic-460ex","ibm,uic";
76		interrupt-controller;
77		cell-index = <2>;
78		dcr-reg = <0x0e0 0x009>;
79		#address-cells = <0>;
80		#size-cells = <0>;
81		#interrupt-cells = <2>;
82		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83		interrupt-parent = <&UIC0>;
84	};
85
86	UIC3: interrupt-controller3 {
87		compatible = "ibm,uic-460ex","ibm,uic";
88		interrupt-controller;
89		cell-index = <3>;
90		dcr-reg = <0x0f0 0x009>;
91		#address-cells = <0>;
92		#size-cells = <0>;
93		#interrupt-cells = <2>;
94		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95		interrupt-parent = <&UIC0>;
96	};
97
98	SDR0: sdr {
99		compatible = "ibm,sdr-460ex";
100		dcr-reg = <0x00e 0x002>;
101	};
102
103	CPR0: cpr {
104		compatible = "ibm,cpr-460ex";
105		dcr-reg = <0x00c 0x002>;
106	};
107
108	L2C0: l2c {
109		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
111			   0x030 0x008>;	/* L2 cache DCR's */
112		cache-line-size = <32>;		/* 32 bytes */
113		cache-size = <262144>;		/* L2, 256K */
114		interrupt-parent = <&UIC1>;
115		interrupts = <11 1>;
116	};
117
118	plb {
119		compatible = "ibm,plb-460ex", "ibm,plb4";
120		#address-cells = <2>;
121		#size-cells = <1>;
122		ranges;
123		clock-frequency = <0>; /* Filled in by U-Boot */
124
125		SDRAM0: sdram {
126			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
127			dcr-reg = <0x010 0x002>;
128		};
129
130		CRYPTO: crypto@180000 {
131			compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
132			reg = <4 0x00180000 0x80400>;
133			interrupt-parent = <&UIC0>;
134			interrupts = <0x1d 0x4>;
135		};
136
137		MAL0: mcmal {
138			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
139			dcr-reg = <0x180 0x062>;
140			num-tx-chans = <2>;
141			num-rx-chans = <16>;
142			#address-cells = <0>;
143			#size-cells = <0>;
144			interrupt-parent = <&UIC2>;
145			interrupts = <	/*TXEOB*/ 0x6 0x4
146					/*RXEOB*/ 0x7 0x4
147					/*SERR*/  0x3 0x4
148					/*TXDE*/  0x4 0x4
149					/*RXDE*/  0x5 0x4>;
150		};
151
152                USB0: ehci@bffd0400 {
153                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
154                        interrupt-parent = <&UIC2>;
155                        interrupts = <0x1d 4>;
156                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
157                };
158
159                USB1: usb@bffd0000 {
160                        compatible = "ohci-le";
161                        reg = <4 0xbffd0000 0x60>;
162                        interrupt-parent = <&UIC2>;
163                        interrupts = <0x1e 4>;
164                };
165
166		POB0: opb {
167			compatible = "ibm,opb-460ex", "ibm,opb";
168			#address-cells = <1>;
169			#size-cells = <1>;
170			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
171			clock-frequency = <0>; /* Filled in by U-Boot */
172
173			EBC0: ebc {
174				compatible = "ibm,ebc-460ex", "ibm,ebc";
175				dcr-reg = <0x012 0x002>;
176				#address-cells = <2>;
177				#size-cells = <1>;
178				clock-frequency = <0>; /* Filled in by U-Boot */
179				/* ranges property is supplied by U-Boot */
180				interrupts = <0x6 0x4>;
181				interrupt-parent = <&UIC1>;
182
183				nor_flash@0,0 {
184					compatible = "amd,s29gl512n", "cfi-flash";
185					bank-width = <2>;
186					reg = <0x00000000 0x00000000 0x04000000>;
187					#address-cells = <1>;
188					#size-cells = <1>;
189					partition@0 {
190						label = "kernel";
191						reg = <0x00000000 0x001e0000>;
192					};
193					partition@1e0000 {
194						label = "dtb";
195						reg = <0x001e0000 0x00020000>;
196					};
197					partition@200000 {
198						label = "ramdisk";
199						reg = <0x00200000 0x01400000>;
200					};
201					partition@1600000 {
202						label = "jffs2";
203						reg = <0x01600000 0x00400000>;
204					};
205					partition@1a00000 {
206						label = "user";
207						reg = <0x01a00000 0x02560000>;
208					};
209					partition@3f60000 {
210						label = "env";
211						reg = <0x03f60000 0x00040000>;
212					};
213					partition@3fa0000 {
214						label = "u-boot";
215						reg = <0x03fa0000 0x00060000>;
216					};
217				};
218			};
219
220			UART0: serial@ef600300 {
221				device_type = "serial";
222				compatible = "ns16550";
223				reg = <0xef600300 0x00000008>;
224				virtual-reg = <0xef600300>;
225				clock-frequency = <0>; /* Filled in by U-Boot */
226				current-speed = <0>; /* Filled in by U-Boot */
227				interrupt-parent = <&UIC1>;
228				interrupts = <0x1 0x4>;
229			};
230
231			UART1: serial@ef600400 {
232				device_type = "serial";
233				compatible = "ns16550";
234				reg = <0xef600400 0x00000008>;
235				virtual-reg = <0xef600400>;
236				clock-frequency = <0>; /* Filled in by U-Boot */
237				current-speed = <0>; /* Filled in by U-Boot */
238				interrupt-parent = <&UIC0>;
239				interrupts = <0x1 0x4>;
240			};
241
242			UART2: serial@ef600500 {
243				device_type = "serial";
244				compatible = "ns16550";
245				reg = <0xef600500 0x00000008>;
246				virtual-reg = <0xef600500>;
247				clock-frequency = <0>; /* Filled in by U-Boot */
248				current-speed = <0>; /* Filled in by U-Boot */
249				interrupt-parent = <&UIC1>;
250				interrupts = <0x1d 0x4>;
251			};
252
253			UART3: serial@ef600600 {
254				device_type = "serial";
255				compatible = "ns16550";
256				reg = <0xef600600 0x00000008>;
257				virtual-reg = <0xef600600>;
258				clock-frequency = <0>; /* Filled in by U-Boot */
259				current-speed = <0>; /* Filled in by U-Boot */
260				interrupt-parent = <&UIC1>;
261				interrupts = <0x1e 0x4>;
262			};
263
264			IIC0: i2c@ef600700 {
265				compatible = "ibm,iic-460ex", "ibm,iic";
266				reg = <0xef600700 0x00000014>;
267				interrupt-parent = <&UIC0>;
268				interrupts = <0x2 0x4>;
269				#address-cells = <1>;
270				#size-cells = <0>;
271                                rtc@68 {
272                                        compatible = "stm,m41t80";
273                                        reg = <0x68>;
274					interrupt-parent = <&UIC2>;
275					interrupts = <0x19 0x8>;
276                                };
277                                sttm@48 {
278                                        compatible = "ad,ad7414";
279                                        reg = <0x48>;
280					interrupt-parent = <&UIC1>;
281					interrupts = <0x14 0x8>;
282                                };
283			};
284
285			IIC1: i2c@ef600800 {
286				compatible = "ibm,iic-460ex", "ibm,iic";
287				reg = <0xef600800 0x00000014>;
288				interrupt-parent = <&UIC0>;
289				interrupts = <0x3 0x4>;
290			};
291
292			ZMII0: emac-zmii@ef600d00 {
293				compatible = "ibm,zmii-460ex", "ibm,zmii";
294				reg = <0xef600d00 0x0000000c>;
295			};
296
297			RGMII0: emac-rgmii@ef601500 {
298				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
299				reg = <0xef601500 0x00000008>;
300				has-mdio;
301			};
302
303			TAH0: emac-tah@ef601350 {
304				compatible = "ibm,tah-460ex", "ibm,tah";
305				reg = <0xef601350 0x00000030>;
306			};
307
308			TAH1: emac-tah@ef601450 {
309				compatible = "ibm,tah-460ex", "ibm,tah";
310				reg = <0xef601450 0x00000030>;
311			};
312
313			EMAC0: ethernet@ef600e00 {
314				device_type = "network";
315				compatible = "ibm,emac-460ex", "ibm,emac4sync";
316				interrupt-parent = <&EMAC0>;
317				interrupts = <0x0 0x1>;
318				#interrupt-cells = <1>;
319				#address-cells = <0>;
320				#size-cells = <0>;
321				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
322						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
323				reg = <0xef600e00 0x000000c4>;
324				local-mac-address = [000000000000]; /* Filled in by U-Boot */
325				mal-device = <&MAL0>;
326				mal-tx-channel = <0>;
327				mal-rx-channel = <0>;
328				cell-index = <0>;
329				max-frame-size = <9000>;
330				rx-fifo-size = <4096>;
331				tx-fifo-size = <2048>;
332				phy-mode = "rgmii";
333				phy-map = <0x00000000>;
334				rgmii-device = <&RGMII0>;
335				rgmii-channel = <0>;
336				tah-device = <&TAH0>;
337				tah-channel = <0>;
338				has-inverted-stacr-oc;
339				has-new-stacr-staopc;
340			};
341
342			EMAC1: ethernet@ef600f00 {
343				device_type = "network";
344				compatible = "ibm,emac-460ex", "ibm,emac4sync";
345				interrupt-parent = <&EMAC1>;
346				interrupts = <0x0 0x1>;
347				#interrupt-cells = <1>;
348				#address-cells = <0>;
349				#size-cells = <0>;
350				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
351						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
352				reg = <0xef600f00 0x000000c4>;
353				local-mac-address = [000000000000]; /* Filled in by U-Boot */
354				mal-device = <&MAL0>;
355				mal-tx-channel = <1>;
356				mal-rx-channel = <8>;
357				cell-index = <1>;
358				max-frame-size = <9000>;
359				rx-fifo-size = <4096>;
360				tx-fifo-size = <2048>;
361				phy-mode = "rgmii";
362				phy-map = <0x00000000>;
363				rgmii-device = <&RGMII0>;
364				rgmii-channel = <1>;
365				tah-device = <&TAH1>;
366				tah-channel = <1>;
367				has-inverted-stacr-oc;
368				has-new-stacr-staopc;
369				mdio-device = <&EMAC0>;
370			};
371		};
372
373		PCIX0: pci@c0ec00000 {
374			device_type = "pci";
375			#interrupt-cells = <1>;
376			#size-cells = <2>;
377			#address-cells = <3>;
378			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
379			primary;
380			large-inbound-windows;
381			enable-msi-hole;
382			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
383			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
384			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
385			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
386			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */
387
388			/* Outbound ranges, one memory and one IO,
389			 * later cannot be changed
390			 */
391			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
392				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
393				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
394
395			/* Inbound 2GB range starting at 0 */
396			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
397
398			/* This drives busses 0 to 0x3f */
399			bus-range = <0x0 0x3f>;
400
401			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
402			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
403			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
404		};
405
406		PCIE0: pciex@d00000000 {
407			device_type = "pci";
408			#interrupt-cells = <1>;
409			#size-cells = <2>;
410			#address-cells = <3>;
411			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
412			primary;
413			port = <0x0>; /* port number */
414			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
415			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
416			dcr-reg = <0x100 0x020>;
417			sdr-base = <0x300>;
418
419			/* Outbound ranges, one memory and one IO,
420			 * later cannot be changed
421			 */
422			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
423				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
424				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
425
426			/* Inbound 2GB range starting at 0 */
427			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
428
429			/* This drives busses 40 to 0x7f */
430			bus-range = <0x40 0x7f>;
431
432			/* Legacy interrupts (note the weird polarity, the bridge seems
433			 * to invert PCIe legacy interrupts).
434			 * We are de-swizzling here because the numbers are actually for
435			 * port of the root complex virtual P2P bridge. But I want
436			 * to avoid putting a node for it in the tree, so the numbers
437			 * below are basically de-swizzled numbers.
438			 * The real slot is on idsel 0, so the swizzling is 1:1
439			 */
440			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
441			interrupt-map = <
442				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
443				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
444				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
445				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
446		};
447
448		PCIE1: pciex@d20000000 {
449			device_type = "pci";
450			#interrupt-cells = <1>;
451			#size-cells = <2>;
452			#address-cells = <3>;
453			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
454			primary;
455			port = <0x1>; /* port number */
456			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
457			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
458			dcr-reg = <0x120 0x020>;
459			sdr-base = <0x340>;
460
461			/* Outbound ranges, one memory and one IO,
462			 * later cannot be changed
463			 */
464			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
465				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
466				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
467
468			/* Inbound 2GB range starting at 0 */
469			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
470
471			/* This drives busses 80 to 0xbf */
472			bus-range = <0x80 0xbf>;
473
474			/* Legacy interrupts (note the weird polarity, the bridge seems
475			 * to invert PCIe legacy interrupts).
476			 * We are de-swizzling here because the numbers are actually for
477			 * port of the root complex virtual P2P bridge. But I want
478			 * to avoid putting a node for it in the tree, so the numbers
479			 * below are basically de-swizzled numbers.
480			 * The real slot is on idsel 0, so the swizzling is 1:1
481			 */
482			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
483			interrupt-map = <
484				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
485				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
486				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
487				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
488		};
489	};
490};
491