18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 48bc4a51dSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 118bc4a51dSStefan Roese/ { 128bc4a51dSStefan Roese #address-cells = <2>; 138bc4a51dSStefan Roese #size-cells = <1>; 148bc4a51dSStefan Roese model = "amcc,canyonlands"; 158bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 168bc4a51dSStefan Roese dcr-parent = <&/cpus/cpu@0>; 178bc4a51dSStefan Roese 188bc4a51dSStefan Roese aliases { 198bc4a51dSStefan Roese ethernet0 = &EMAC0; 208bc4a51dSStefan Roese ethernet1 = &EMAC1; 218bc4a51dSStefan Roese serial0 = &UART0; 228bc4a51dSStefan Roese serial1 = &UART1; 238bc4a51dSStefan Roese }; 248bc4a51dSStefan Roese 258bc4a51dSStefan Roese cpus { 268bc4a51dSStefan Roese #address-cells = <1>; 278bc4a51dSStefan Roese #size-cells = <0>; 288bc4a51dSStefan Roese 298bc4a51dSStefan Roese cpu@0 { 308bc4a51dSStefan Roese device_type = "cpu"; 318bc4a51dSStefan Roese model = "PowerPC,460EX"; 328bc4a51dSStefan Roese reg = <0>; 338bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 348bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 358bc4a51dSStefan Roese i-cache-line-size = <20>; 368bc4a51dSStefan Roese d-cache-line-size = <20>; 378bc4a51dSStefan Roese i-cache-size = <8000>; 388bc4a51dSStefan Roese d-cache-size = <8000>; 398bc4a51dSStefan Roese dcr-controller; 408bc4a51dSStefan Roese dcr-access-method = "native"; 418bc4a51dSStefan Roese }; 428bc4a51dSStefan Roese }; 438bc4a51dSStefan Roese 448bc4a51dSStefan Roese memory { 458bc4a51dSStefan Roese device_type = "memory"; 468bc4a51dSStefan Roese reg = <0 0 0>; /* Filled in by U-Boot */ 478bc4a51dSStefan Roese }; 488bc4a51dSStefan Roese 498bc4a51dSStefan Roese UIC0: interrupt-controller0 { 508bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 518bc4a51dSStefan Roese interrupt-controller; 528bc4a51dSStefan Roese cell-index = <0>; 538bc4a51dSStefan Roese dcr-reg = <0c0 009>; 548bc4a51dSStefan Roese #address-cells = <0>; 558bc4a51dSStefan Roese #size-cells = <0>; 568bc4a51dSStefan Roese #interrupt-cells = <2>; 578bc4a51dSStefan Roese }; 588bc4a51dSStefan Roese 598bc4a51dSStefan Roese UIC1: interrupt-controller1 { 608bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 618bc4a51dSStefan Roese interrupt-controller; 628bc4a51dSStefan Roese cell-index = <1>; 638bc4a51dSStefan Roese dcr-reg = <0d0 009>; 648bc4a51dSStefan Roese #address-cells = <0>; 658bc4a51dSStefan Roese #size-cells = <0>; 668bc4a51dSStefan Roese #interrupt-cells = <2>; 678bc4a51dSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 688bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 698bc4a51dSStefan Roese }; 708bc4a51dSStefan Roese 718bc4a51dSStefan Roese UIC2: interrupt-controller2 { 728bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 738bc4a51dSStefan Roese interrupt-controller; 748bc4a51dSStefan Roese cell-index = <2>; 758bc4a51dSStefan Roese dcr-reg = <0e0 009>; 768bc4a51dSStefan Roese #address-cells = <0>; 778bc4a51dSStefan Roese #size-cells = <0>; 788bc4a51dSStefan Roese #interrupt-cells = <2>; 798bc4a51dSStefan Roese interrupts = <a 4 b 4>; /* cascade */ 808bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 818bc4a51dSStefan Roese }; 828bc4a51dSStefan Roese 838bc4a51dSStefan Roese UIC3: interrupt-controller3 { 848bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 858bc4a51dSStefan Roese interrupt-controller; 868bc4a51dSStefan Roese cell-index = <3>; 878bc4a51dSStefan Roese dcr-reg = <0f0 009>; 888bc4a51dSStefan Roese #address-cells = <0>; 898bc4a51dSStefan Roese #size-cells = <0>; 908bc4a51dSStefan Roese #interrupt-cells = <2>; 918bc4a51dSStefan Roese interrupts = <10 4 11 4>; /* cascade */ 928bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 938bc4a51dSStefan Roese }; 948bc4a51dSStefan Roese 958bc4a51dSStefan Roese SDR0: sdr { 968bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 978bc4a51dSStefan Roese dcr-reg = <00e 002>; 988bc4a51dSStefan Roese }; 998bc4a51dSStefan Roese 1008bc4a51dSStefan Roese CPR0: cpr { 1018bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 1028bc4a51dSStefan Roese dcr-reg = <00c 002>; 1038bc4a51dSStefan Roese }; 1048bc4a51dSStefan Roese 1058bc4a51dSStefan Roese plb { 1068bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1078bc4a51dSStefan Roese #address-cells = <2>; 1088bc4a51dSStefan Roese #size-cells = <1>; 1098bc4a51dSStefan Roese ranges; 1108bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1118bc4a51dSStefan Roese 1128bc4a51dSStefan Roese SDRAM0: sdram { 1138bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 1148bc4a51dSStefan Roese dcr-reg = <010 2>; 1158bc4a51dSStefan Roese }; 1168bc4a51dSStefan Roese 1178bc4a51dSStefan Roese MAL0: mcmal { 1188bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 1198bc4a51dSStefan Roese dcr-reg = <180 62>; 1208bc4a51dSStefan Roese num-tx-chans = <2>; 1218bc4a51dSStefan Roese num-rx-chans = <10>; 1228bc4a51dSStefan Roese #address-cells = <0>; 1238bc4a51dSStefan Roese #size-cells = <0>; 1248bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 1258bc4a51dSStefan Roese interrupts = < /*TXEOB*/ 6 4 1268bc4a51dSStefan Roese /*RXEOB*/ 7 4 1278bc4a51dSStefan Roese /*SERR*/ 3 4 1288bc4a51dSStefan Roese /*TXDE*/ 4 4 1298bc4a51dSStefan Roese /*RXDE*/ 5 4>; 1308bc4a51dSStefan Roese }; 1318bc4a51dSStefan Roese 1328bc4a51dSStefan Roese POB0: opb { 1338bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1348bc4a51dSStefan Roese #address-cells = <1>; 1358bc4a51dSStefan Roese #size-cells = <1>; 1368bc4a51dSStefan Roese ranges = <b0000000 4 b0000000 50000000>; 1378bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1388bc4a51dSStefan Roese 1398bc4a51dSStefan Roese EBC0: ebc { 1408bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 1418bc4a51dSStefan Roese dcr-reg = <012 2>; 1428bc4a51dSStefan Roese #address-cells = <2>; 1438bc4a51dSStefan Roese #size-cells = <1>; 1448bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1458bc4a51dSStefan Roese interrupts = <6 4>; 1468bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1478bc4a51dSStefan Roese }; 1488bc4a51dSStefan Roese 1498bc4a51dSStefan Roese UART0: serial@ef600300 { 1508bc4a51dSStefan Roese device_type = "serial"; 1518bc4a51dSStefan Roese compatible = "ns16550"; 1528bc4a51dSStefan Roese reg = <ef600300 8>; 1538bc4a51dSStefan Roese virtual-reg = <ef600300>; 1548bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1558bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1568bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1578bc4a51dSStefan Roese interrupts = <1 4>; 1588bc4a51dSStefan Roese }; 1598bc4a51dSStefan Roese 1608bc4a51dSStefan Roese UART1: serial@ef600400 { 1618bc4a51dSStefan Roese device_type = "serial"; 1628bc4a51dSStefan Roese compatible = "ns16550"; 1638bc4a51dSStefan Roese reg = <ef600400 8>; 1648bc4a51dSStefan Roese virtual-reg = <ef600400>; 1658bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1668bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1678bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 1688bc4a51dSStefan Roese interrupts = <1 4>; 1698bc4a51dSStefan Roese }; 1708bc4a51dSStefan Roese 1718bc4a51dSStefan Roese UART2: serial@ef600500 { 1728bc4a51dSStefan Roese device_type = "serial"; 1738bc4a51dSStefan Roese compatible = "ns16550"; 1748bc4a51dSStefan Roese reg = <ef600500 8>; 1758bc4a51dSStefan Roese virtual-reg = <ef600500>; 1768bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1778bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1788bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1798bc4a51dSStefan Roese interrupts = <1d 4>; 1808bc4a51dSStefan Roese }; 1818bc4a51dSStefan Roese 1828bc4a51dSStefan Roese UART3: serial@ef600600 { 1838bc4a51dSStefan Roese device_type = "serial"; 1848bc4a51dSStefan Roese compatible = "ns16550"; 1858bc4a51dSStefan Roese reg = <ef600600 8>; 1868bc4a51dSStefan Roese virtual-reg = <ef600600>; 1878bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1888bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1898bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1908bc4a51dSStefan Roese interrupts = <1e 4>; 1918bc4a51dSStefan Roese }; 1928bc4a51dSStefan Roese 1938bc4a51dSStefan Roese IIC0: i2c@ef600700 { 1948bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 1958bc4a51dSStefan Roese reg = <ef600700 14>; 1968bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 1978bc4a51dSStefan Roese interrupts = <2 4>; 1988bc4a51dSStefan Roese }; 1998bc4a51dSStefan Roese 2008bc4a51dSStefan Roese IIC1: i2c@ef600800 { 2018bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 2028bc4a51dSStefan Roese reg = <ef600800 14>; 2038bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 2048bc4a51dSStefan Roese interrupts = <3 4>; 2058bc4a51dSStefan Roese }; 2068bc4a51dSStefan Roese 2078bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 2088bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 2098bc4a51dSStefan Roese reg = <ef600d00 c>; 2108bc4a51dSStefan Roese }; 2118bc4a51dSStefan Roese 2128bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 2138bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 2148bc4a51dSStefan Roese reg = <ef601500 8>; 2158bc4a51dSStefan Roese has-mdio; 2168bc4a51dSStefan Roese }; 2178bc4a51dSStefan Roese 218a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 219a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 220a6190a84SStefan Roese reg = <ef601350 30>; 221a6190a84SStefan Roese }; 222a6190a84SStefan Roese 223a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 224a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 225a6190a84SStefan Roese reg = <ef601450 30>; 226a6190a84SStefan Roese }; 227a6190a84SStefan Roese 2288bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 2298bc4a51dSStefan Roese device_type = "network"; 2308bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2318bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 2328bc4a51dSStefan Roese interrupts = <0 1>; 2338bc4a51dSStefan Roese #interrupt-cells = <1>; 2348bc4a51dSStefan Roese #address-cells = <0>; 2358bc4a51dSStefan Roese #size-cells = <0>; 2368bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 10 4 2378bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 14 4>; 2388bc4a51dSStefan Roese reg = <ef600e00 70>; 2398bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2408bc4a51dSStefan Roese mal-device = <&MAL0>; 2418bc4a51dSStefan Roese mal-tx-channel = <0>; 2428bc4a51dSStefan Roese mal-rx-channel = <0>; 2438bc4a51dSStefan Roese cell-index = <0>; 2448bc4a51dSStefan Roese max-frame-size = <2328>; 2458bc4a51dSStefan Roese rx-fifo-size = <1000>; 2468bc4a51dSStefan Roese tx-fifo-size = <800>; 2478bc4a51dSStefan Roese phy-mode = "rgmii"; 2488bc4a51dSStefan Roese phy-map = <00000000>; 2498bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 2508bc4a51dSStefan Roese rgmii-channel = <0>; 251a6190a84SStefan Roese tah-device = <&TAH0>; 252a6190a84SStefan Roese tah-channel = <0>; 2538bc4a51dSStefan Roese has-inverted-stacr-oc; 2548bc4a51dSStefan Roese has-new-stacr-staopc; 2558bc4a51dSStefan Roese }; 2568bc4a51dSStefan Roese 2578bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 2588bc4a51dSStefan Roese device_type = "network"; 2598bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2608bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 2618bc4a51dSStefan Roese interrupts = <0 1>; 2628bc4a51dSStefan Roese #interrupt-cells = <1>; 2638bc4a51dSStefan Roese #address-cells = <0>; 2648bc4a51dSStefan Roese #size-cells = <0>; 2658bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 11 4 2668bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 15 4>; 2678bc4a51dSStefan Roese reg = <ef600f00 70>; 2688bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2698bc4a51dSStefan Roese mal-device = <&MAL0>; 2708bc4a51dSStefan Roese mal-tx-channel = <1>; 2718bc4a51dSStefan Roese mal-rx-channel = <8>; 2728bc4a51dSStefan Roese cell-index = <1>; 2738bc4a51dSStefan Roese max-frame-size = <2328>; 2748bc4a51dSStefan Roese rx-fifo-size = <1000>; 2758bc4a51dSStefan Roese tx-fifo-size = <800>; 2768bc4a51dSStefan Roese phy-mode = "rgmii"; 2778bc4a51dSStefan Roese phy-map = <00000000>; 2788bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 2798bc4a51dSStefan Roese rgmii-channel = <1>; 280a6190a84SStefan Roese tah-device = <&TAH1>; 281a6190a84SStefan Roese tah-channel = <1>; 2828bc4a51dSStefan Roese has-inverted-stacr-oc; 2838bc4a51dSStefan Roese has-new-stacr-staopc; 284a6190a84SStefan Roese mdio-device = <&EMAC0>; 2858bc4a51dSStefan Roese }; 2868bc4a51dSStefan Roese }; 2878bc4a51dSStefan Roese 2888bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 2898bc4a51dSStefan Roese device_type = "pci"; 2908bc4a51dSStefan Roese #interrupt-cells = <1>; 2918bc4a51dSStefan Roese #size-cells = <2>; 2928bc4a51dSStefan Roese #address-cells = <3>; 2938bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 2948bc4a51dSStefan Roese primary; 2958bc4a51dSStefan Roese large-inbound-windows; 2968bc4a51dSStefan Roese enable-msi-hole; 2978bc4a51dSStefan Roese reg = <c 0ec00000 8 /* Config space access */ 2988bc4a51dSStefan Roese 0 0 0 /* no IACK cycles */ 2998bc4a51dSStefan Roese c 0ed00000 4 /* Special cycles */ 3008bc4a51dSStefan Roese c 0ec80000 100 /* Internal registers */ 3018bc4a51dSStefan Roese c 0ec80100 fc>; /* Internal messaging registers */ 3028bc4a51dSStefan Roese 3038bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3048bc4a51dSStefan Roese * later cannot be changed 3058bc4a51dSStefan Roese */ 3068bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 3078bc4a51dSStefan Roese 01000000 0 00000000 0000000c 08000000 0 00010000>; 3088bc4a51dSStefan Roese 3098bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 3108bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 3118bc4a51dSStefan Roese 3128bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 3138bc4a51dSStefan Roese bus-range = <0 3f>; 3148bc4a51dSStefan Roese 3158bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 3168bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 0>; 3178bc4a51dSStefan Roese interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 3188bc4a51dSStefan Roese }; 3198bc4a51dSStefan Roese 3208bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 3218bc4a51dSStefan Roese device_type = "pci"; 3228bc4a51dSStefan Roese #interrupt-cells = <1>; 3238bc4a51dSStefan Roese #size-cells = <2>; 3248bc4a51dSStefan Roese #address-cells = <3>; 3258bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 3268bc4a51dSStefan Roese primary; 3278bc4a51dSStefan Roese port = <0>; /* port number */ 3288bc4a51dSStefan Roese reg = <d 00000000 20000000 /* Config space access */ 3298bc4a51dSStefan Roese c 08010000 00001000>; /* Registers */ 3308bc4a51dSStefan Roese dcr-reg = <100 020>; 3318bc4a51dSStefan Roese sdr-base = <300>; 3328bc4a51dSStefan Roese 3338bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3348bc4a51dSStefan Roese * later cannot be changed 3358bc4a51dSStefan Roese */ 3368bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 3378bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80000000 0 00010000>; 3388bc4a51dSStefan Roese 3398bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 3408bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 3418bc4a51dSStefan Roese 3428bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 3438bc4a51dSStefan Roese bus-range = <40 7f>; 3448bc4a51dSStefan Roese 3458bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3468bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 3478bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 3488bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 3498bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3508bc4a51dSStefan Roese * below are basically de-swizzled numbers. 3518bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3528bc4a51dSStefan Roese */ 3538bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 3548bc4a51dSStefan Roese interrupt-map = < 3558bc4a51dSStefan Roese 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 3568bc4a51dSStefan Roese 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 3578bc4a51dSStefan Roese 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 3588bc4a51dSStefan Roese 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 3598bc4a51dSStefan Roese }; 3608bc4a51dSStefan Roese 3618bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 3628bc4a51dSStefan Roese device_type = "pci"; 3638bc4a51dSStefan Roese #interrupt-cells = <1>; 3648bc4a51dSStefan Roese #size-cells = <2>; 3658bc4a51dSStefan Roese #address-cells = <3>; 3668bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 3678bc4a51dSStefan Roese primary; 3688bc4a51dSStefan Roese port = <1>; /* port number */ 3698bc4a51dSStefan Roese reg = <d 20000000 20000000 /* Config space access */ 3708bc4a51dSStefan Roese c 08011000 00001000>; /* Registers */ 3718bc4a51dSStefan Roese dcr-reg = <120 020>; 3728bc4a51dSStefan Roese sdr-base = <340>; 3738bc4a51dSStefan Roese 3748bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3758bc4a51dSStefan Roese * later cannot be changed 3768bc4a51dSStefan Roese */ 3778bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 3788bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80010000 0 00010000>; 3798bc4a51dSStefan Roese 3808bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 3818bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 3828bc4a51dSStefan Roese 3838bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 3848bc4a51dSStefan Roese bus-range = <80 bf>; 3858bc4a51dSStefan Roese 3868bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3878bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 3888bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 3898bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 3908bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3918bc4a51dSStefan Roese * below are basically de-swizzled numbers. 3928bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3938bc4a51dSStefan Roese */ 3948bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 3958bc4a51dSStefan Roese interrupt-map = < 3968bc4a51dSStefan Roese 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 3978bc4a51dSStefan Roese 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 3988bc4a51dSStefan Roese 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 3998bc4a51dSStefan Roese 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 4008bc4a51dSStefan Roese }; 4018bc4a51dSStefan Roese }; 4028bc4a51dSStefan Roese}; 403