18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 488eeb72eSStefan Roese * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 138bc4a51dSStefan Roese/ { 148bc4a51dSStefan Roese #address-cells = <2>; 158bc4a51dSStefan Roese #size-cells = <1>; 168bc4a51dSStefan Roese model = "amcc,canyonlands"; 178bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 198bc4a51dSStefan Roese 208bc4a51dSStefan Roese aliases { 218bc4a51dSStefan Roese ethernet0 = &EMAC0; 228bc4a51dSStefan Roese ethernet1 = &EMAC1; 238bc4a51dSStefan Roese serial0 = &UART0; 248bc4a51dSStefan Roese serial1 = &UART1; 258bc4a51dSStefan Roese }; 268bc4a51dSStefan Roese 278bc4a51dSStefan Roese cpus { 288bc4a51dSStefan Roese #address-cells = <1>; 298bc4a51dSStefan Roese #size-cells = <0>; 308bc4a51dSStefan Roese 318bc4a51dSStefan Roese cpu@0 { 328bc4a51dSStefan Roese device_type = "cpu"; 338bc4a51dSStefan Roese model = "PowerPC,460EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 358bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 368bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <32768>; 4071f34979SDavid Gibson d-cache-size = <32768>; 418bc4a51dSStefan Roese dcr-controller; 428bc4a51dSStefan Roese dcr-access-method = "native"; 43cd85400aSStefan Roese next-level-cache = <&L2C0>; 448bc4a51dSStefan Roese }; 458bc4a51dSStefan Roese }; 468bc4a51dSStefan Roese 478bc4a51dSStefan Roese memory { 488bc4a51dSStefan Roese device_type = "memory"; 4971f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 508bc4a51dSStefan Roese }; 518bc4a51dSStefan Roese 528bc4a51dSStefan Roese UIC0: interrupt-controller0 { 538bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 548bc4a51dSStefan Roese interrupt-controller; 558bc4a51dSStefan Roese cell-index = <0>; 5671f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 578bc4a51dSStefan Roese #address-cells = <0>; 588bc4a51dSStefan Roese #size-cells = <0>; 598bc4a51dSStefan Roese #interrupt-cells = <2>; 608bc4a51dSStefan Roese }; 618bc4a51dSStefan Roese 628bc4a51dSStefan Roese UIC1: interrupt-controller1 { 638bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 648bc4a51dSStefan Roese interrupt-controller; 658bc4a51dSStefan Roese cell-index = <1>; 6671f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 678bc4a51dSStefan Roese #address-cells = <0>; 688bc4a51dSStefan Roese #size-cells = <0>; 698bc4a51dSStefan Roese #interrupt-cells = <2>; 7071f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 718bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 728bc4a51dSStefan Roese }; 738bc4a51dSStefan Roese 748bc4a51dSStefan Roese UIC2: interrupt-controller2 { 758bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 768bc4a51dSStefan Roese interrupt-controller; 778bc4a51dSStefan Roese cell-index = <2>; 7871f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 798bc4a51dSStefan Roese #address-cells = <0>; 808bc4a51dSStefan Roese #size-cells = <0>; 818bc4a51dSStefan Roese #interrupt-cells = <2>; 8271f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 838bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 848bc4a51dSStefan Roese }; 858bc4a51dSStefan Roese 868bc4a51dSStefan Roese UIC3: interrupt-controller3 { 878bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 888bc4a51dSStefan Roese interrupt-controller; 898bc4a51dSStefan Roese cell-index = <3>; 9071f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 918bc4a51dSStefan Roese #address-cells = <0>; 928bc4a51dSStefan Roese #size-cells = <0>; 938bc4a51dSStefan Roese #interrupt-cells = <2>; 9471f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 958bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 968bc4a51dSStefan Roese }; 978bc4a51dSStefan Roese 988bc4a51dSStefan Roese SDR0: sdr { 998bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 10071f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 1018bc4a51dSStefan Roese }; 1028bc4a51dSStefan Roese 1038bc4a51dSStefan Roese CPR0: cpr { 1048bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 10571f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 1068bc4a51dSStefan Roese }; 1078bc4a51dSStefan Roese 108ee2ffd8bSVictor Gallardo CPM0: cpm { 109ee2ffd8bSVictor Gallardo compatible = "ibm,cpm"; 110ee2ffd8bSVictor Gallardo dcr-access-method = "native"; 111ee2ffd8bSVictor Gallardo dcr-reg = <0x160 0x003>; 112ee2ffd8bSVictor Gallardo unused-units = <0x00000100>; 113ee2ffd8bSVictor Gallardo idle-doze = <0x02000000>; 114ee2ffd8bSVictor Gallardo standby = <0xfeff791d>; 115ee2ffd8bSVictor Gallardo }; 116ee2ffd8bSVictor Gallardo 117cd85400aSStefan Roese L2C0: l2c { 118cd85400aSStefan Roese compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 119cd85400aSStefan Roese dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 120cd85400aSStefan Roese 0x030 0x008>; /* L2 cache DCR's */ 121cd85400aSStefan Roese cache-line-size = <32>; /* 32 bytes */ 122cd85400aSStefan Roese cache-size = <262144>; /* L2, 256K */ 123cd85400aSStefan Roese interrupt-parent = <&UIC1>; 124cd85400aSStefan Roese interrupts = <11 1>; 125cd85400aSStefan Roese }; 126cd85400aSStefan Roese 1278bc4a51dSStefan Roese plb { 1288bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1298bc4a51dSStefan Roese #address-cells = <2>; 1308bc4a51dSStefan Roese #size-cells = <1>; 1318bc4a51dSStefan Roese ranges; 1328bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1338bc4a51dSStefan Roese 1348bc4a51dSStefan Roese SDRAM0: sdram { 1358bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 13671f34979SDavid Gibson dcr-reg = <0x010 0x002>; 1378bc4a51dSStefan Roese }; 1388bc4a51dSStefan Roese 139049359d6SJames Hsiao CRYPTO: crypto@180000 { 140049359d6SJames Hsiao compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; 141049359d6SJames Hsiao reg = <4 0x00180000 0x80400>; 142049359d6SJames Hsiao interrupt-parent = <&UIC0>; 143049359d6SJames Hsiao interrupts = <0x1d 0x4>; 144049359d6SJames Hsiao }; 145049359d6SJames Hsiao 14657308499SMike Williams HWRNG: hwrng@110000 { 14757308499SMike Williams compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; 14857308499SMike Williams reg = <4 0x00110000 0x50>; 14957308499SMike Williams }; 15057308499SMike Williams 1518bc4a51dSStefan Roese MAL0: mcmal { 1528bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 15371f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1548bc4a51dSStefan Roese num-tx-chans = <2>; 15571f34979SDavid Gibson num-rx-chans = <16>; 1568bc4a51dSStefan Roese #address-cells = <0>; 1578bc4a51dSStefan Roese #size-cells = <0>; 1588bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 15971f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 16071f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 16171f34979SDavid Gibson /*SERR*/ 0x3 0x4 16271f34979SDavid Gibson /*TXDE*/ 0x4 0x4 16371f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 1648bc4a51dSStefan Roese }; 1658bc4a51dSStefan Roese 166018f76ecSBenjamin Herrenschmidt USB0: ehci@bffd0400 { 167018f76ecSBenjamin Herrenschmidt compatible = "ibm,usb-ehci-460ex", "usb-ehci"; 168018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 169018f76ecSBenjamin Herrenschmidt interrupts = <0x1d 4>; 170018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; 171018f76ecSBenjamin Herrenschmidt }; 172018f76ecSBenjamin Herrenschmidt 173018f76ecSBenjamin Herrenschmidt USB1: usb@bffd0000 { 174018f76ecSBenjamin Herrenschmidt compatible = "ohci-le"; 175018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0000 0x60>; 176018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 177018f76ecSBenjamin Herrenschmidt interrupts = <0x1e 4>; 178018f76ecSBenjamin Herrenschmidt }; 179018f76ecSBenjamin Herrenschmidt 180c89b3458STirumala Marri USBOTG0: usbotg@bff80000 { 181c89b3458STirumala Marri compatible = "amcc,dwc-otg"; 182c89b3458STirumala Marri reg = <0x4 0xbff80000 0x10000>; 183c89b3458STirumala Marri interrupt-parent = <&USBOTG0>; 184c89b3458STirumala Marri #interrupt-cells = <1>; 185c89b3458STirumala Marri #address-cells = <0>; 186c89b3458STirumala Marri #size-cells = <0>; 187c89b3458STirumala Marri interrupts = <0x0 0x1 0x2>; 188c89b3458STirumala Marri interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4 189c89b3458STirumala Marri /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8 190c89b3458STirumala Marri /* DMA */ 0x2 &UIC0 0xc 0x4>; 191c89b3458STirumala Marri }; 192c89b3458STirumala Marri 19331fc0bd4SRupjyoti Sarmah SATA0: sata@bffd1000 { 19431fc0bd4SRupjyoti Sarmah compatible = "amcc,sata-460ex"; 19531fc0bd4SRupjyoti Sarmah reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; 19631fc0bd4SRupjyoti Sarmah interrupt-parent = <&UIC3>; 19731fc0bd4SRupjyoti Sarmah interrupts = <0x0 0x4 /* SATA */ 19831fc0bd4SRupjyoti Sarmah 0x5 0x4>; /* AHBDMA */ 19931fc0bd4SRupjyoti Sarmah }; 20031fc0bd4SRupjyoti Sarmah 2018bc4a51dSStefan Roese POB0: opb { 2028bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 2038bc4a51dSStefan Roese #address-cells = <1>; 2048bc4a51dSStefan Roese #size-cells = <1>; 20571f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 2068bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2078bc4a51dSStefan Roese 2088bc4a51dSStefan Roese EBC0: ebc { 2098bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 21071f34979SDavid Gibson dcr-reg = <0x012 0x002>; 2118bc4a51dSStefan Roese #address-cells = <2>; 2128bc4a51dSStefan Roese #size-cells = <1>; 2138bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2145020231bSStefan Roese /* ranges property is supplied by U-Boot */ 21571f34979SDavid Gibson interrupts = <0x6 0x4>; 2168bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 2175020231bSStefan Roese 2185020231bSStefan Roese nor_flash@0,0 { 2195020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 2205020231bSStefan Roese bank-width = <2>; 22171f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 2225020231bSStefan Roese #address-cells = <1>; 2235020231bSStefan Roese #size-cells = <1>; 2245020231bSStefan Roese partition@0 { 2255020231bSStefan Roese label = "kernel"; 22671f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 2275020231bSStefan Roese }; 2285020231bSStefan Roese partition@1e0000 { 2295020231bSStefan Roese label = "dtb"; 23071f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 2315020231bSStefan Roese }; 2325020231bSStefan Roese partition@200000 { 2335020231bSStefan Roese label = "ramdisk"; 23471f34979SDavid Gibson reg = <0x00200000 0x01400000>; 2355020231bSStefan Roese }; 2365020231bSStefan Roese partition@1600000 { 2375020231bSStefan Roese label = "jffs2"; 23871f34979SDavid Gibson reg = <0x01600000 0x00400000>; 2395020231bSStefan Roese }; 2405020231bSStefan Roese partition@1a00000 { 2415020231bSStefan Roese label = "user"; 24271f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 2435020231bSStefan Roese }; 2445020231bSStefan Roese partition@3f60000 { 2455020231bSStefan Roese label = "env"; 24671f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 2475020231bSStefan Roese }; 2485020231bSStefan Roese partition@3fa0000 { 2495020231bSStefan Roese label = "u-boot"; 25071f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 2515020231bSStefan Roese }; 2525020231bSStefan Roese }; 25388eeb72eSStefan Roese 2548960f7ffSRupjyoti Sarmah cpld@2,0 { 2558960f7ffSRupjyoti Sarmah compatible = "amcc,ppc460ex-bcsr"; 2568960f7ffSRupjyoti Sarmah reg = <2 0x0 0x9>; 2578960f7ffSRupjyoti Sarmah }; 2588960f7ffSRupjyoti Sarmah 25988eeb72eSStefan Roese ndfc@3,0 { 26088eeb72eSStefan Roese compatible = "ibm,ndfc"; 26188eeb72eSStefan Roese reg = <0x00000003 0x00000000 0x00002000>; 26288eeb72eSStefan Roese ccr = <0x00001000>; 26388eeb72eSStefan Roese bank-settings = <0x80002222>; 26488eeb72eSStefan Roese #address-cells = <1>; 26588eeb72eSStefan Roese #size-cells = <1>; 26688eeb72eSStefan Roese 26788eeb72eSStefan Roese nand { 26888eeb72eSStefan Roese #address-cells = <1>; 26988eeb72eSStefan Roese #size-cells = <1>; 27088eeb72eSStefan Roese 27188eeb72eSStefan Roese partition@0 { 27288eeb72eSStefan Roese label = "u-boot"; 27388eeb72eSStefan Roese reg = <0x00000000 0x00100000>; 27488eeb72eSStefan Roese }; 27588eeb72eSStefan Roese partition@100000 { 27688eeb72eSStefan Roese label = "user"; 27788eeb72eSStefan Roese reg = <0x00000000 0x03f00000>; 27888eeb72eSStefan Roese }; 27988eeb72eSStefan Roese }; 28088eeb72eSStefan Roese }; 2818bc4a51dSStefan Roese }; 2828bc4a51dSStefan Roese 2838bc4a51dSStefan Roese UART0: serial@ef600300 { 2848bc4a51dSStefan Roese device_type = "serial"; 2858bc4a51dSStefan Roese compatible = "ns16550"; 28671f34979SDavid Gibson reg = <0xef600300 0x00000008>; 28771f34979SDavid Gibson virtual-reg = <0xef600300>; 2888bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2898bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2908bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 29171f34979SDavid Gibson interrupts = <0x1 0x4>; 2928bc4a51dSStefan Roese }; 2938bc4a51dSStefan Roese 2948bc4a51dSStefan Roese UART1: serial@ef600400 { 2958bc4a51dSStefan Roese device_type = "serial"; 2968bc4a51dSStefan Roese compatible = "ns16550"; 29771f34979SDavid Gibson reg = <0xef600400 0x00000008>; 29871f34979SDavid Gibson virtual-reg = <0xef600400>; 2998bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 3008bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 3018bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 30271f34979SDavid Gibson interrupts = <0x1 0x4>; 3038bc4a51dSStefan Roese }; 3048bc4a51dSStefan Roese 3058bc4a51dSStefan Roese IIC0: i2c@ef600700 { 3068bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 30771f34979SDavid Gibson reg = <0xef600700 0x00000014>; 3088bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 30971f34979SDavid Gibson interrupts = <0x2 0x4>; 310018f76ecSBenjamin Herrenschmidt #address-cells = <1>; 311018f76ecSBenjamin Herrenschmidt #size-cells = <0>; 312018f76ecSBenjamin Herrenschmidt rtc@68 { 313018f76ecSBenjamin Herrenschmidt compatible = "stm,m41t80"; 314018f76ecSBenjamin Herrenschmidt reg = <0x68>; 315018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 316018f76ecSBenjamin Herrenschmidt interrupts = <0x19 0x8>; 317018f76ecSBenjamin Herrenschmidt }; 318018f76ecSBenjamin Herrenschmidt sttm@48 { 319018f76ecSBenjamin Herrenschmidt compatible = "ad,ad7414"; 320018f76ecSBenjamin Herrenschmidt reg = <0x48>; 321018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC1>; 322018f76ecSBenjamin Herrenschmidt interrupts = <0x14 0x8>; 323018f76ecSBenjamin Herrenschmidt }; 3248bc4a51dSStefan Roese }; 3258bc4a51dSStefan Roese 3268bc4a51dSStefan Roese IIC1: i2c@ef600800 { 3278bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 32871f34979SDavid Gibson reg = <0xef600800 0x00000014>; 3298bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 33071f34979SDavid Gibson interrupts = <0x3 0x4>; 3318bc4a51dSStefan Roese }; 3328bc4a51dSStefan Roese 3338960f7ffSRupjyoti Sarmah GPIO0: gpio@ef600b00 { 3348960f7ffSRupjyoti Sarmah compatible = "ibm,ppc4xx-gpio"; 3358960f7ffSRupjyoti Sarmah reg = <0xef600b00 0x00000048>; 3368960f7ffSRupjyoti Sarmah gpio-controller; 3378960f7ffSRupjyoti Sarmah }; 3388960f7ffSRupjyoti Sarmah 3398bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 3408bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 34171f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 3428bc4a51dSStefan Roese }; 3438bc4a51dSStefan Roese 3448bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 3458bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 34671f34979SDavid Gibson reg = <0xef601500 0x00000008>; 3478bc4a51dSStefan Roese has-mdio; 3488bc4a51dSStefan Roese }; 3498bc4a51dSStefan Roese 350a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 351a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 35271f34979SDavid Gibson reg = <0xef601350 0x00000030>; 353a6190a84SStefan Roese }; 354a6190a84SStefan Roese 355a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 356a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 35771f34979SDavid Gibson reg = <0xef601450 0x00000030>; 358a6190a84SStefan Roese }; 359a6190a84SStefan Roese 3608bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 3618bc4a51dSStefan Roese device_type = "network"; 36205781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3638bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 36471f34979SDavid Gibson interrupts = <0x0 0x1>; 3658bc4a51dSStefan Roese #interrupt-cells = <1>; 3668bc4a51dSStefan Roese #address-cells = <0>; 3678bc4a51dSStefan Roese #size-cells = <0>; 36871f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 36971f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 37005781ccdSGrant Erickson reg = <0xef600e00 0x000000c4>; 3718bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3728bc4a51dSStefan Roese mal-device = <&MAL0>; 3738bc4a51dSStefan Roese mal-tx-channel = <0>; 3748bc4a51dSStefan Roese mal-rx-channel = <0>; 3758bc4a51dSStefan Roese cell-index = <0>; 37671f34979SDavid Gibson max-frame-size = <9000>; 37771f34979SDavid Gibson rx-fifo-size = <4096>; 37871f34979SDavid Gibson tx-fifo-size = <2048>; 379835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 3808bc4a51dSStefan Roese phy-mode = "rgmii"; 38171f34979SDavid Gibson phy-map = <0x00000000>; 3828bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3838bc4a51dSStefan Roese rgmii-channel = <0>; 384a6190a84SStefan Roese tah-device = <&TAH0>; 385a6190a84SStefan Roese tah-channel = <0>; 3868bc4a51dSStefan Roese has-inverted-stacr-oc; 3878bc4a51dSStefan Roese has-new-stacr-staopc; 3888bc4a51dSStefan Roese }; 3898bc4a51dSStefan Roese 3908bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 3918bc4a51dSStefan Roese device_type = "network"; 39205781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3938bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 39471f34979SDavid Gibson interrupts = <0x0 0x1>; 3958bc4a51dSStefan Roese #interrupt-cells = <1>; 3968bc4a51dSStefan Roese #address-cells = <0>; 3978bc4a51dSStefan Roese #size-cells = <0>; 39871f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 39971f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 40005781ccdSGrant Erickson reg = <0xef600f00 0x000000c4>; 4018bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 4028bc4a51dSStefan Roese mal-device = <&MAL0>; 4038bc4a51dSStefan Roese mal-tx-channel = <1>; 4048bc4a51dSStefan Roese mal-rx-channel = <8>; 4058bc4a51dSStefan Roese cell-index = <1>; 40671f34979SDavid Gibson max-frame-size = <9000>; 40771f34979SDavid Gibson rx-fifo-size = <4096>; 40871f34979SDavid Gibson tx-fifo-size = <2048>; 409835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 4108bc4a51dSStefan Roese phy-mode = "rgmii"; 41171f34979SDavid Gibson phy-map = <0x00000000>; 4128bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 4138bc4a51dSStefan Roese rgmii-channel = <1>; 414a6190a84SStefan Roese tah-device = <&TAH1>; 415a6190a84SStefan Roese tah-channel = <1>; 4168bc4a51dSStefan Roese has-inverted-stacr-oc; 4178bc4a51dSStefan Roese has-new-stacr-staopc; 418a6190a84SStefan Roese mdio-device = <&EMAC0>; 4198bc4a51dSStefan Roese }; 4208bc4a51dSStefan Roese }; 4218bc4a51dSStefan Roese 4228bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 4238bc4a51dSStefan Roese device_type = "pci"; 4248bc4a51dSStefan Roese #interrupt-cells = <1>; 4258bc4a51dSStefan Roese #size-cells = <2>; 4268bc4a51dSStefan Roese #address-cells = <3>; 4278bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 4288bc4a51dSStefan Roese primary; 4298bc4a51dSStefan Roese large-inbound-windows; 4308bc4a51dSStefan Roese enable-msi-hole; 43171f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 43271f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 43371f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 43471f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 43571f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 4368bc4a51dSStefan Roese 4378bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4388bc4a51dSStefan Roese * later cannot be changed 4398bc4a51dSStefan Roese */ 44071f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 44184d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 44271f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 4438bc4a51dSStefan Roese 4448bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 44571f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4468bc4a51dSStefan Roese 4478bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 44871f34979SDavid Gibson bus-range = <0x0 0x3f>; 4498bc4a51dSStefan Roese 4508bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 45171f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 45271f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 4538bc4a51dSStefan Roese }; 4548bc4a51dSStefan Roese 4558bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 4568bc4a51dSStefan Roese device_type = "pci"; 4578bc4a51dSStefan Roese #interrupt-cells = <1>; 4588bc4a51dSStefan Roese #size-cells = <2>; 4598bc4a51dSStefan Roese #address-cells = <3>; 4608bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4618bc4a51dSStefan Roese primary; 46271f34979SDavid Gibson port = <0x0>; /* port number */ 46371f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 46471f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 46571f34979SDavid Gibson dcr-reg = <0x100 0x020>; 46671f34979SDavid Gibson sdr-base = <0x300>; 4678bc4a51dSStefan Roese 4688bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4698bc4a51dSStefan Roese * later cannot be changed 4708bc4a51dSStefan Roese */ 47171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 47284d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 47371f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 4748bc4a51dSStefan Roese 4758bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 47671f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4778bc4a51dSStefan Roese 4788bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 47971f34979SDavid Gibson bus-range = <0x40 0x7f>; 4808bc4a51dSStefan Roese 4818bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4828bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4838bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4848bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4858bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4868bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4878bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4888bc4a51dSStefan Roese */ 48971f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4908bc4a51dSStefan Roese interrupt-map = < 49171f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 49271f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 49371f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 49471f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 4958bc4a51dSStefan Roese }; 4968bc4a51dSStefan Roese 4978bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 4988bc4a51dSStefan Roese device_type = "pci"; 4998bc4a51dSStefan Roese #interrupt-cells = <1>; 5008bc4a51dSStefan Roese #size-cells = <2>; 5018bc4a51dSStefan Roese #address-cells = <3>; 5028bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 5038bc4a51dSStefan Roese primary; 50471f34979SDavid Gibson port = <0x1>; /* port number */ 50571f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 50671f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 50771f34979SDavid Gibson dcr-reg = <0x120 0x020>; 50871f34979SDavid Gibson sdr-base = <0x340>; 5098bc4a51dSStefan Roese 5108bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 5118bc4a51dSStefan Roese * later cannot be changed 5128bc4a51dSStefan Roese */ 51371f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 51484d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 51571f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 5168bc4a51dSStefan Roese 5178bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 51871f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 5198bc4a51dSStefan Roese 5208bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 52171f34979SDavid Gibson bus-range = <0x80 0xbf>; 5228bc4a51dSStefan Roese 5238bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 5248bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 5258bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 5268bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 5278bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 5288bc4a51dSStefan Roese * below are basically de-swizzled numbers. 5298bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 5308bc4a51dSStefan Roese */ 53171f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 5328bc4a51dSStefan Roese interrupt-map = < 53371f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 53471f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 53571f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 53671f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 5378bc4a51dSStefan Roese }; 5383fb79338SRupjyoti Sarmah 5393fb79338SRupjyoti Sarmah MSI: ppc4xx-msi@C10000000 { 5403fb79338SRupjyoti Sarmah compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; 5413fb79338SRupjyoti Sarmah reg = < 0xC 0x10000000 0x100>; 5423fb79338SRupjyoti Sarmah sdr-base = <0x36C>; 5433fb79338SRupjyoti Sarmah msi-data = <0x00000000>; 5443fb79338SRupjyoti Sarmah msi-mask = <0x44440000>; 5453fb79338SRupjyoti Sarmah interrupt-count = <3>; 5463fb79338SRupjyoti Sarmah interrupts = <0 1 2 3>; 5473fb79338SRupjyoti Sarmah interrupt-parent = <&UIC3>; 5483fb79338SRupjyoti Sarmah #interrupt-cells = <1>; 5493fb79338SRupjyoti Sarmah #address-cells = <0>; 5503fb79338SRupjyoti Sarmah #size-cells = <0>; 5513fb79338SRupjyoti Sarmah interrupt-map = <0 &UIC3 0x18 1 5523fb79338SRupjyoti Sarmah 1 &UIC3 0x19 1 5533fb79338SRupjyoti Sarmah 2 &UIC3 0x1A 1 5543fb79338SRupjyoti Sarmah 3 &UIC3 0x1B 1>; 5553fb79338SRupjyoti Sarmah }; 5568bc4a51dSStefan Roese }; 5578bc4a51dSStefan Roese}; 558