1/*
2 * Device Tree for Bluestone (APM821xx) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27	#address-cells = <2>;
28	#size-cells = <1>;
29	model = "apm,bluestone";
30	compatible = "apm,bluestone";
31	dcr-parent = <&{/cpus/cpu@0}>;
32
33	aliases {
34		ethernet0 = &EMAC0;
35		serial0 = &UART0;
36		serial1 = &UART1;
37	};
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42
43		cpu@0 {
44			device_type = "cpu";
45			model = "PowerPC,apm821xx";
46			reg = <0x00000000>;
47			clock-frequency = <0>; /* Filled in by U-Boot */
48			timebase-frequency = <0>; /* Filled in by U-Boot */
49			i-cache-line-size = <32>;
50			d-cache-line-size = <32>;
51			i-cache-size = <32768>;
52			d-cache-size = <32768>;
53			dcr-controller;
54			dcr-access-method = "native";
55			next-level-cache = <&L2C0>;
56		};
57	};
58
59	memory {
60		device_type = "memory";
61		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
62	};
63
64	UIC0: interrupt-controller0 {
65		compatible = "ibm,uic";
66		interrupt-controller;
67		cell-index = <0>;
68		dcr-reg = <0x0c0 0x009>;
69		#address-cells = <0>;
70		#size-cells = <0>;
71		#interrupt-cells = <2>;
72	};
73
74	UIC1: interrupt-controller1 {
75		compatible = "ibm,uic";
76		interrupt-controller;
77		cell-index = <1>;
78		dcr-reg = <0x0d0 0x009>;
79		#address-cells = <0>;
80		#size-cells = <0>;
81		#interrupt-cells = <2>;
82		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83		interrupt-parent = <&UIC0>;
84	};
85
86	UIC2: interrupt-controller2 {
87		compatible = "ibm,uic";
88		interrupt-controller;
89		cell-index = <2>;
90		dcr-reg = <0x0e0 0x009>;
91		#address-cells = <0>;
92		#size-cells = <0>;
93		#interrupt-cells = <2>;
94		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
95		interrupt-parent = <&UIC0>;
96	};
97
98	UIC3: interrupt-controller3 {
99		compatible = "ibm,uic";
100		interrupt-controller;
101		cell-index = <3>;
102		dcr-reg = <0x0f0 0x009>;
103		#address-cells = <0>;
104		#size-cells = <0>;
105		#interrupt-cells = <2>;
106		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
107		interrupt-parent = <&UIC0>;
108	};
109
110	OCM: ocm@400040000 {
111		compatible = "ibm,ocm";
112		status = "ok";
113		cell-index = <1>;
114		/* configured in U-Boot */
115		reg = <4 0x00040000 0x8000>; /* 32K */
116	};
117
118	SDR0: sdr {
119		compatible = "ibm,sdr-apm821xx";
120		dcr-reg = <0x00e 0x002>;
121	};
122
123	CPR0: cpr {
124		compatible = "ibm,cpr-apm821xx";
125		dcr-reg = <0x00c 0x002>;
126	};
127
128	L2C0: l2c {
129		compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
130		dcr-reg = <0x020 0x008
131			   0x030 0x008>;
132		cache-line-size = <32>;
133		cache-size = <262144>;
134		interrupt-parent = <&UIC1>;
135		interrupts = <11 1>;
136	};
137
138	plb {
139		compatible = "ibm,plb4";
140		#address-cells = <2>;
141		#size-cells = <1>;
142		ranges;
143		clock-frequency = <0>; /* Filled in by U-Boot */
144
145		SDRAM0: sdram {
146			compatible = "ibm,sdram-apm821xx";
147			dcr-reg = <0x010 0x002>;
148		};
149
150		MAL0: mcmal {
151			compatible = "ibm,mcmal2";
152			descriptor-memory = "ocm";
153			dcr-reg = <0x180 0x062>;
154			num-tx-chans = <1>;
155			num-rx-chans = <1>;
156			#address-cells = <0>;
157			#size-cells = <0>;
158			interrupt-parent = <&UIC2>;
159			interrupts = <	/*TXEOB*/ 0x6 0x4
160					/*RXEOB*/ 0x7 0x4
161					/*SERR*/  0x3 0x4
162					/*TXDE*/  0x4 0x4
163					/*RXDE*/  0x5 0x4>;
164		};
165
166		POB0: opb {
167			compatible = "ibm,opb";
168			#address-cells = <1>;
169			#size-cells = <1>;
170			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
171			clock-frequency = <0>; /* Filled in by U-Boot */
172
173			EBC0: ebc {
174				compatible = "ibm,ebc";
175				dcr-reg = <0x012 0x002>;
176				#address-cells = <2>;
177				#size-cells = <1>;
178				clock-frequency = <0>; /* Filled in by U-Boot */
179				/* ranges property is supplied by U-Boot */
180				ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
181				interrupts = <0x6 0x4>;
182				interrupt-parent = <&UIC1>;
183
184				nor_flash@0,0 {
185					compatible = "amd,s29gl512n", "cfi-flash";
186					bank-width = <2>;
187					reg = <0x00000000 0x00000000 0x00400000>;
188					#address-cells = <1>;
189					#size-cells = <1>;
190					partition@0 {
191						label = "kernel";
192						reg = <0x00000000 0x00180000>;
193					};
194					partition@180000 {
195						label = "env";
196						reg = <0x00180000 0x00020000>;
197					};
198					partition@1a0000 {
199						label = "u-boot";
200						reg = <0x001a0000 0x00060000>;
201					};
202				};
203
204				ndfc@1,0 {
205					compatible = "ibm,ndfc";
206					reg = <0x00000003 0x00000000 0x00002000>;
207					ccr = <0x00001000>;
208					bank-settings = <0x80002222>;
209					#address-cells = <1>;
210					#size-cells = <1>;
211					/* 2Gb Nand Flash */
212					nand {
213						#address-cells = <1>;
214						#size-cells = <1>;
215
216						partition@0 {
217							label = "firmware";
218							reg   = <0x00000000 0x00C00000>;
219						};
220						partition@c00000 {
221							label = "environment";
222							reg   = <0x00C00000 0x00B00000>;
223						};
224						partition@1700000 {
225							label = "kernel";
226							reg   = <0x01700000 0x00E00000>;
227						};
228						partition@2500000 {
229							label = "root";
230							reg   = <0x02500000 0x08200000>;
231						};
232						partition@a700000 {
233							label = "device-tree";
234							reg   = <0x0A700000 0x00B00000>;
235						};
236						partition@b200000 {
237							label = "config";
238							reg   = <0x0B200000 0x00D00000>;
239						};
240						partition@bf00000 {
241							label = "diag";
242							reg   = <0x0BF00000 0x00C00000>;
243						};
244						partition@cb00000 {
245							label = "vendor";
246							reg   = <0x0CB00000 0x3500000>;
247						};
248					};
249				};
250			};
251
252			UART0: serial@ef600300 {
253				device_type = "serial";
254				compatible = "ns16550";
255				reg = <0xef600300 0x00000008>;
256				virtual-reg = <0xef600300>;
257				clock-frequency = <0>; /* Filled in by U-Boot */
258				current-speed = <0>; /* Filled in by U-Boot */
259				interrupt-parent = <&UIC1>;
260				interrupts = <0x1 0x4>;
261			};
262
263			UART1: serial@ef600400 {
264				device_type = "serial";
265				compatible = "ns16550";
266				reg = <0xef600400 0x00000008>;
267				virtual-reg = <0xef600400>;
268				clock-frequency = <0>; /* Filled in by U-Boot */
269				current-speed = <0>; /* Filled in by U-Boot */
270				interrupt-parent = <&UIC0>;
271				interrupts = <0x1 0x4>;
272			};
273
274			IIC0: i2c@ef600700 {
275				compatible = "ibm,iic";
276				reg = <0xef600700 0x00000014>;
277				interrupt-parent = <&UIC0>;
278				interrupts = <0x2 0x4>;
279				#address-cells = <1>;
280				#size-cells = <0>;
281				rtc@68 {
282					compatible = "st,m41t80";
283					reg = <0x68>;
284					interrupt-parent = <&UIC0>;
285					interrupts = <0x9 0x8>;
286				};
287				sttm@4C {
288					compatible = "adm,adm1032";
289					reg = <0x4C>;
290					interrupt-parent = <&UIC1>;
291					interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
292				};
293			};
294
295			IIC1: i2c@ef600800 {
296				compatible = "ibm,iic";
297				reg = <0xef600800 0x00000014>;
298				interrupt-parent = <&UIC0>;
299				interrupts = <0x3 0x4>;
300			};
301
302			RGMII0: emac-rgmii@ef601500 {
303				compatible = "ibm,rgmii";
304				reg = <0xef601500 0x00000008>;
305				has-mdio;
306			};
307
308			TAH0: emac-tah@ef601350 {
309				compatible = "ibm,tah";
310				reg = <0xef601350 0x00000030>;
311			};
312
313			EMAC0: ethernet@ef600c00 {
314				device_type = "network";
315				compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
316				interrupt-parent = <&EMAC0>;
317				interrupts = <0x0 0x1>;
318				#interrupt-cells = <1>;
319				#address-cells = <0>;
320				#size-cells = <0>;
321				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
322						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
323				reg = <0xef600c00 0x000000c4>;
324				local-mac-address = [000000000000]; /* Filled in by U-Boot */
325				mal-device = <&MAL0>;
326				mal-tx-channel = <0>;
327				mal-rx-channel = <0>;
328				cell-index = <0>;
329				max-frame-size = <9000>;
330				rx-fifo-size = <16384>;
331				tx-fifo-size = <2048>;
332				phy-mode = "rgmii";
333				phy-map = <0x00000000>;
334				rgmii-device = <&RGMII0>;
335				rgmii-channel = <0>;
336				tah-device = <&TAH0>;
337				tah-channel = <0>;
338				has-inverted-stacr-oc;
339				has-new-stacr-staopc;
340			};
341		};
342
343		PCIE0: pciex@d00000000 {
344			device_type = "pci";
345			#interrupt-cells = <1>;
346			#size-cells = <2>;
347			#address-cells = <3>;
348			compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
349			primary;
350			port = <0x0>; /* port number */
351			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
352			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
353			dcr-reg = <0x100 0x020>;
354			sdr-base = <0x300>;
355
356			/* Outbound ranges, one memory and one IO,
357			 * later cannot be changed
358			 */
359			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
360				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
361				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
362
363			/* Inbound 2GB range starting at 0 */
364			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
365
366			/* This drives busses 40 to 0x7f */
367			bus-range = <0x40 0x7f>;
368
369			/* Legacy interrupts (note the weird polarity, the bridge seems
370			 * to invert PCIe legacy interrupts).
371			 * We are de-swizzling here because the numbers are actually for
372			 * port of the root complex virtual P2P bridge. But I want
373			 * to avoid putting a node for it in the tree, so the numbers
374			 * below are basically de-swizzled numbers.
375			 * The real slot is on idsel 0, so the swizzling is 1:1
376			 */
377			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
378			interrupt-map = <
379				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
380				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
381				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
382				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
383		};
384
385		MSI: ppc4xx-msi@C10000000 {
386			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
387			reg = < 0xC 0x10000000 0x100
388				0xC 0x10000000 0x100>;
389			sdr-base = <0x36C>;
390			msi-data = <0x00004440>;
391			msi-mask = <0x0000ffe0>;
392			interrupts =<0 1 2 3 4 5 6 7>;
393			interrupt-parent = <&MSI>;
394			#interrupt-cells = <1>;
395			#address-cells = <0>;
396			#size-cells = <0>;
397			msi-available-ranges = <0x0 0x100>;
398			interrupt-map = <
399				0 &UIC3 0x18 1
400				1 &UIC3 0x19 1
401				2 &UIC3 0x1A 1
402				3 &UIC3 0x1B 1
403				4 &UIC3 0x1C 1
404				5 &UIC3 0x1D 1
405				6 &UIC3 0x1E 1
406				7 &UIC3 0x1F 1
407			>;
408		};
409	};
410};
411