1/* 2 * Device Tree Source for AMCC Arches (dual 460GT board) 3 * 4 * (C) Copyright 2008 Applied Micro Circuits Corporation 5 * Victor Gallardo <vgallardo@amcc.com> 6 * Adam Graham <agraham@amcc.com> 7 * 8 * Based on the glacier.dts file 9 * Stefan Roese <sr@denx.de> 10 * Copyright 2008 DENX Software Engineering 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31/dts-v1/; 32 33/ { 34 #address-cells = <2>; 35 #size-cells = <1>; 36 model = "amcc,arches"; 37 compatible = "amcc,arches"; 38 dcr-parent = <&{/cpus/cpu@0}>; 39 40 aliases { 41 ethernet0 = &EMAC0; 42 ethernet1 = &EMAC1; 43 ethernet2 = &EMAC2; 44 serial0 = &UART0; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu@0 { 52 device_type = "cpu"; 53 model = "PowerPC,460GT"; 54 reg = <0x00000000>; 55 clock-frequency = <0>; /* Filled in by U-Boot */ 56 timebase-frequency = <0>; /* Filled in by U-Boot */ 57 i-cache-line-size = <32>; 58 d-cache-line-size = <32>; 59 i-cache-size = <32768>; 60 d-cache-size = <32768>; 61 dcr-controller; 62 dcr-access-method = "native"; 63 }; 64 }; 65 66 memory { 67 device_type = "memory"; 68 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 69 }; 70 71 UIC0: interrupt-controller0 { 72 compatible = "ibm,uic-460gt","ibm,uic"; 73 interrupt-controller; 74 cell-index = <0>; 75 dcr-reg = <0x0c0 0x009>; 76 #address-cells = <0>; 77 #size-cells = <0>; 78 #interrupt-cells = <2>; 79 }; 80 81 UIC1: interrupt-controller1 { 82 compatible = "ibm,uic-460gt","ibm,uic"; 83 interrupt-controller; 84 cell-index = <1>; 85 dcr-reg = <0x0d0 0x009>; 86 #address-cells = <0>; 87 #size-cells = <0>; 88 #interrupt-cells = <2>; 89 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 90 interrupt-parent = <&UIC0>; 91 }; 92 93 UIC2: interrupt-controller2 { 94 compatible = "ibm,uic-460gt","ibm,uic"; 95 interrupt-controller; 96 cell-index = <2>; 97 dcr-reg = <0x0e0 0x009>; 98 #address-cells = <0>; 99 #size-cells = <0>; 100 #interrupt-cells = <2>; 101 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 102 interrupt-parent = <&UIC0>; 103 }; 104 105 UIC3: interrupt-controller3 { 106 compatible = "ibm,uic-460gt","ibm,uic"; 107 interrupt-controller; 108 cell-index = <3>; 109 dcr-reg = <0x0f0 0x009>; 110 #address-cells = <0>; 111 #size-cells = <0>; 112 #interrupt-cells = <2>; 113 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 114 interrupt-parent = <&UIC0>; 115 }; 116 117 SDR0: sdr { 118 compatible = "ibm,sdr-460gt"; 119 dcr-reg = <0x00e 0x002>; 120 }; 121 122 CPR0: cpr { 123 compatible = "ibm,cpr-460gt"; 124 dcr-reg = <0x00c 0x002>; 125 }; 126 127 plb { 128 compatible = "ibm,plb-460gt", "ibm,plb4"; 129 #address-cells = <2>; 130 #size-cells = <1>; 131 ranges; 132 clock-frequency = <0>; /* Filled in by U-Boot */ 133 134 SDRAM0: sdram { 135 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 136 dcr-reg = <0x010 0x002>; 137 }; 138 139 MAL0: mcmal { 140 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 141 dcr-reg = <0x180 0x062>; 142 num-tx-chans = <3>; 143 num-rx-chans = <24>; 144 #address-cells = <0>; 145 #size-cells = <0>; 146 interrupt-parent = <&UIC2>; 147 interrupts = < /*TXEOB*/ 0x6 0x4 148 /*RXEOB*/ 0x7 0x4 149 /*SERR*/ 0x3 0x4 150 /*TXDE*/ 0x4 0x4 151 /*RXDE*/ 0x5 0x4>; 152 desc-base-addr-high = <0x8>; 153 }; 154 155 POB0: opb { 156 compatible = "ibm,opb-460gt", "ibm,opb"; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 160 clock-frequency = <0>; /* Filled in by U-Boot */ 161 162 EBC0: ebc { 163 compatible = "ibm,ebc-460gt", "ibm,ebc"; 164 dcr-reg = <0x012 0x002>; 165 #address-cells = <2>; 166 #size-cells = <1>; 167 clock-frequency = <0>; /* Filled in by U-Boot */ 168 /* ranges property is supplied by U-Boot */ 169 interrupts = <0x6 0x4>; 170 interrupt-parent = <&UIC1>; 171 }; 172 173 UART0: serial@ef600300 { 174 device_type = "serial"; 175 compatible = "ns16550"; 176 reg = <0xef600300 0x00000008>; 177 virtual-reg = <0xef600300>; 178 clock-frequency = <0>; /* Filled in by U-Boot */ 179 current-speed = <0>; /* Filled in by U-Boot */ 180 interrupt-parent = <&UIC1>; 181 interrupts = <0x1 0x4>; 182 }; 183 184 IIC0: i2c@ef600700 { 185 compatible = "ibm,iic-460gt", "ibm,iic"; 186 reg = <0xef600700 0x00000014>; 187 interrupt-parent = <&UIC0>; 188 interrupts = <0x2 0x4>; 189 }; 190 191 IIC1: i2c@ef600800 { 192 compatible = "ibm,iic-460gt", "ibm,iic"; 193 reg = <0xef600800 0x00000014>; 194 interrupt-parent = <&UIC0>; 195 interrupts = <0x3 0x4>; 196 }; 197 198 TAH0: emac-tah@ef601350 { 199 compatible = "ibm,tah-460gt", "ibm,tah"; 200 reg = <0xef601350 0x00000030>; 201 }; 202 203 TAH1: emac-tah@ef601450 { 204 compatible = "ibm,tah-460gt", "ibm,tah"; 205 reg = <0xef601450 0x00000030>; 206 }; 207 208 EMAC0: ethernet@ef600e00 { 209 device_type = "network"; 210 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 211 interrupt-parent = <&EMAC0>; 212 interrupts = <0x0 0x1>; 213 #interrupt-cells = <1>; 214 #address-cells = <0>; 215 #size-cells = <0>; 216 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 217 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 218 reg = <0xef600e00 0x000000c4>; 219 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 220 mal-device = <&MAL0>; 221 mal-tx-channel = <0>; 222 mal-rx-channel = <0>; 223 cell-index = <0>; 224 max-frame-size = <9000>; 225 rx-fifo-size = <4096>; 226 tx-fifo-size = <2048>; 227 phy-mode = "sgmii"; 228 phy-map = <0xffffffff>; 229 gpcs-address = <0x0000000a>; 230 tah-device = <&TAH0>; 231 tah-channel = <0>; 232 has-inverted-stacr-oc; 233 has-new-stacr-staopc; 234 }; 235 236 EMAC1: ethernet@ef600f00 { 237 device_type = "network"; 238 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 239 interrupt-parent = <&EMAC1>; 240 interrupts = <0x0 0x1>; 241 #interrupt-cells = <1>; 242 #address-cells = <0>; 243 #size-cells = <0>; 244 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 245 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 246 reg = <0xef600f00 0x000000c4>; 247 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 248 mal-device = <&MAL0>; 249 mal-tx-channel = <1>; 250 mal-rx-channel = <8>; 251 cell-index = <1>; 252 max-frame-size = <9000>; 253 rx-fifo-size = <4096>; 254 tx-fifo-size = <2048>; 255 phy-mode = "sgmii"; 256 phy-map = <0x00000000>; 257 gpcs-address = <0x0000000b>; 258 tah-device = <&TAH1>; 259 tah-channel = <1>; 260 has-inverted-stacr-oc; 261 has-new-stacr-staopc; 262 mdio-device = <&EMAC0>; 263 }; 264 265 EMAC2: ethernet@ef601100 { 266 device_type = "network"; 267 compatible = "ibm,emac-460gt", "ibm,emac4sync"; 268 interrupt-parent = <&EMAC2>; 269 interrupts = <0x0 0x1>; 270 #interrupt-cells = <1>; 271 #address-cells = <0>; 272 #size-cells = <0>; 273 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 274 /*Wake*/ 0x1 &UIC2 0x16 0x4>; 275 reg = <0xef601100 0x000000c4>; 276 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 277 mal-device = <&MAL0>; 278 mal-tx-channel = <2>; 279 mal-rx-channel = <16>; 280 cell-index = <2>; 281 max-frame-size = <9000>; 282 rx-fifo-size = <4096>; 283 tx-fifo-size = <2048>; 284 phy-mode = "sgmii"; 285 phy-map = <0x00000001>; 286 gpcs-address = <0x0000000C>; 287 has-inverted-stacr-oc; 288 has-new-stacr-staopc; 289 mdio-device = <&EMAC0>; 290 }; 291 }; 292 }; 293}; 294