1667b504aSStefan Roese/*
2667b504aSStefan Roese * a3m071 board Device Tree Source
3667b504aSStefan Roese *
4667b504aSStefan Roese * Copyright 2012 Stefan Roese <sr@denx.de>
5667b504aSStefan Roese *
6667b504aSStefan Roese * Copyright (C) 2011 DENX Software Engineering GmbH
7667b504aSStefan Roese * Heiko Schocher <hs@denx.de>
8667b504aSStefan Roese *
9667b504aSStefan Roese * Copyright (C) 2007 Semihalf
10667b504aSStefan Roese * Marian Balakowicz <m8@semihalf.com>
11667b504aSStefan Roese *
12667b504aSStefan Roese * This program is free software; you can redistribute  it and/or modify it
13667b504aSStefan Roese * under  the terms of  the GNU General  Public License as published by the
14667b504aSStefan Roese * Free Software Foundation;  either version 2 of the  License, or (at your
15667b504aSStefan Roese * option) any later version.
16667b504aSStefan Roese */
17667b504aSStefan Roese
18667b504aSStefan Roese/include/ "mpc5200b.dtsi"
19667b504aSStefan Roese
20667b504aSStefan Roese/ {
21667b504aSStefan Roese	model = "anonymous,a3m071";
22667b504aSStefan Roese	compatible = "anonymous,a3m071";
23667b504aSStefan Roese
24667b504aSStefan Roese	soc5200@f0000000 {
25667b504aSStefan Roese		#address-cells = <1>;
26667b504aSStefan Roese		#size-cells = <1>;
27667b504aSStefan Roese		compatible = "fsl,mpc5200b-immr";
28667b504aSStefan Roese		ranges = <0 0xf0000000 0x0000c000>;
29667b504aSStefan Roese		reg = <0xf0000000 0x00000100>;
30667b504aSStefan Roese		bus-frequency = <0>; /* From boot loader */
31667b504aSStefan Roese		system-frequency = <0>; /* From boot loader */
32667b504aSStefan Roese
33667b504aSStefan Roese		timer@600 {
34667b504aSStefan Roese			fsl,has-wdt;
35667b504aSStefan Roese		};
36667b504aSStefan Roese
37667b504aSStefan Roese		spi@f00 {
38667b504aSStefan Roese			status = "disabled";
39667b504aSStefan Roese		};
40667b504aSStefan Roese
41667b504aSStefan Roese		usb: usb@1000 {
42667b504aSStefan Roese			status = "disabled";
43667b504aSStefan Roese		};
44667b504aSStefan Roese
45667b504aSStefan Roese		psc@2000 {
46667b504aSStefan Roese			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
47667b504aSStefan Roese			reg = <0x2000 0x100>;
48667b504aSStefan Roese			interrupts = <2 1 0>;
49667b504aSStefan Roese		};
50667b504aSStefan Roese
51667b504aSStefan Roese		psc@2200 {
52667b504aSStefan Roese			status = "disabled";
53667b504aSStefan Roese		};
54667b504aSStefan Roese
55667b504aSStefan Roese		psc@2400 {
56667b504aSStefan Roese			status = "disabled";
57667b504aSStefan Roese		};
58667b504aSStefan Roese
59667b504aSStefan Roese		psc@2600 {
60667b504aSStefan Roese			status = "disabled";
61667b504aSStefan Roese		};
62667b504aSStefan Roese
63667b504aSStefan Roese		psc@2800 {
64667b504aSStefan Roese			status = "disabled";
65667b504aSStefan Roese		};
66667b504aSStefan Roese
67667b504aSStefan Roese		psc@2c00 {		// PSC6
68667b504aSStefan Roese			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
69667b504aSStefan Roese			reg = <0x2c00 0x100>;
70667b504aSStefan Roese			interrupts = <2 4 0>;
71667b504aSStefan Roese		};
72667b504aSStefan Roese
73667b504aSStefan Roese		ethernet@3000 {
74667b504aSStefan Roese			phy-handle = <&phy0>;
75667b504aSStefan Roese		};
76667b504aSStefan Roese
77667b504aSStefan Roese		mdio@3000 {
78667b504aSStefan Roese			phy0: ethernet-phy@3 {
79667b504aSStefan Roese				reg = <0x03>;
80667b504aSStefan Roese			};
81667b504aSStefan Roese		};
82667b504aSStefan Roese
83667b504aSStefan Roese		ata@3a00 {
84667b504aSStefan Roese			status = "disabled";
85667b504aSStefan Roese		};
86667b504aSStefan Roese
87667b504aSStefan Roese		i2c@3d00 {
88667b504aSStefan Roese			status = "disabled";
89667b504aSStefan Roese		};
90667b504aSStefan Roese
91667b504aSStefan Roese		i2c@3d40 {
92667b504aSStefan Roese			status = "disabled";
93667b504aSStefan Roese		};
94667b504aSStefan Roese	};
95667b504aSStefan Roese
96667b504aSStefan Roese	localbus {
97667b504aSStefan Roese		compatible = "fsl,mpc5200b-lpb","simple-bus";
98667b504aSStefan Roese		#address-cells = <2>;
99667b504aSStefan Roese		#size-cells = <1>;
100667b504aSStefan Roese		ranges = <0 0 0xfc000000 0x02000000
101667b504aSStefan Roese			  3 0 0xe9000000 0x00080000
102667b504aSStefan Roese			  5 0 0xe8000000 0x00010000>;
103667b504aSStefan Roese
104667b504aSStefan Roese		flash@0,0 {
105667b504aSStefan Roese			#address-cells = <1>;
106667b504aSStefan Roese			#size-cells = <1>;
107667b504aSStefan Roese			reg = <0 0x0 0x02000000>;
108667b504aSStefan Roese			compatible = "cfi-flash";
109667b504aSStefan Roese			bank-width = <2>;
110667b504aSStefan Roese			partition@0x0 {
111667b504aSStefan Roese				label = "u-boot";
112667b504aSStefan Roese				reg = <0x00000000 0x00040000>;
113667b504aSStefan Roese				read-only;
114667b504aSStefan Roese			};
115667b504aSStefan Roese			partition@0x00040000 {
116667b504aSStefan Roese				label = "env";
117667b504aSStefan Roese				reg = <0x00040000 0x00020000>;
118667b504aSStefan Roese			};
119667b504aSStefan Roese			partition@0x00060000 {
120667b504aSStefan Roese				label = "dtb";
121667b504aSStefan Roese				reg = <0x00060000 0x00020000>;
122667b504aSStefan Roese			};
123667b504aSStefan Roese			partition@0x00080000 {
124667b504aSStefan Roese				label = "kernel";
125667b504aSStefan Roese				reg = <0x00080000 0x00500000>;
126667b504aSStefan Roese			};
127667b504aSStefan Roese			partition@0x00580000 {
128667b504aSStefan Roese				label = "root";
129667b504aSStefan Roese				reg = <0x00580000 0x00A80000>;
130667b504aSStefan Roese			};
131667b504aSStefan Roese		};
132667b504aSStefan Roese
133667b504aSStefan Roese		fpga@3,0 {
134667b504aSStefan Roese			compatible = "anonymous,a3m071-fpga";
135667b504aSStefan Roese			reg = <3 0x0 0x00080000
136667b504aSStefan Roese			       5 0x0 0x00010000>;
137667b504aSStefan Roese			interrupts = <0 0 3>;  /* level low */
138667b504aSStefan Roese		};
139667b504aSStefan Roese	};
140667b504aSStefan Roese
141667b504aSStefan Roese	pci@f0000d00 {
142667b504aSStefan Roese		status = "disabled";
143667b504aSStefan Roese	};
144667b504aSStefan Roese};
145