12874c5fdSThomas Gleixner// SPDX-License-Identifier: GPL-2.0-or-later
2667b504aSStefan Roese/*
3667b504aSStefan Roese * a3m071 board Device Tree Source
4667b504aSStefan Roese *
5667b504aSStefan Roese * Copyright 2012 Stefan Roese <sr@denx.de>
6667b504aSStefan Roese *
7667b504aSStefan Roese * Copyright (C) 2011 DENX Software Engineering GmbH
8667b504aSStefan Roese * Heiko Schocher <hs@denx.de>
9667b504aSStefan Roese *
10667b504aSStefan Roese * Copyright (C) 2007 Semihalf
11667b504aSStefan Roese * Marian Balakowicz <m8@semihalf.com>
12667b504aSStefan Roese */
13667b504aSStefan Roese
14667b504aSStefan Roese/include/ "mpc5200b.dtsi"
15667b504aSStefan Roese
16fa59f178SGrant Likely&gpt0 { fsl,has-wdt; };
17fa59f178SGrant Likely
18667b504aSStefan Roese/ {
19667b504aSStefan Roese	model = "anonymous,a3m071";
20667b504aSStefan Roese	compatible = "anonymous,a3m071";
21667b504aSStefan Roese
22667b504aSStefan Roese	soc5200@f0000000 {
23667b504aSStefan Roese		#address-cells = <1>;
24667b504aSStefan Roese		#size-cells = <1>;
25667b504aSStefan Roese		compatible = "fsl,mpc5200b-immr";
26667b504aSStefan Roese		ranges = <0 0xf0000000 0x0000c000>;
27667b504aSStefan Roese		reg = <0xf0000000 0x00000100>;
28667b504aSStefan Roese		bus-frequency = <0>; /* From boot loader */
29667b504aSStefan Roese		system-frequency = <0>; /* From boot loader */
30667b504aSStefan Roese
31667b504aSStefan Roese		spi@f00 {
32667b504aSStefan Roese			status = "disabled";
33667b504aSStefan Roese		};
34667b504aSStefan Roese
35667b504aSStefan Roese		usb: usb@1000 {
36667b504aSStefan Roese			status = "disabled";
37667b504aSStefan Roese		};
38667b504aSStefan Roese
39667b504aSStefan Roese		psc@2000 {
40667b504aSStefan Roese			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
41667b504aSStefan Roese			reg = <0x2000 0x100>;
42667b504aSStefan Roese			interrupts = <2 1 0>;
43667b504aSStefan Roese		};
44667b504aSStefan Roese
45667b504aSStefan Roese		psc@2200 {
46667b504aSStefan Roese			status = "disabled";
47667b504aSStefan Roese		};
48667b504aSStefan Roese
49667b504aSStefan Roese		psc@2400 {
50667b504aSStefan Roese			status = "disabled";
51667b504aSStefan Roese		};
52667b504aSStefan Roese
53667b504aSStefan Roese		psc@2600 {
54667b504aSStefan Roese			status = "disabled";
55667b504aSStefan Roese		};
56667b504aSStefan Roese
57667b504aSStefan Roese		psc@2800 {
58667b504aSStefan Roese			status = "disabled";
59667b504aSStefan Roese		};
60667b504aSStefan Roese
61667b504aSStefan Roese		psc@2c00 {		// PSC6
62667b504aSStefan Roese			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
63667b504aSStefan Roese			reg = <0x2c00 0x100>;
64667b504aSStefan Roese			interrupts = <2 4 0>;
65667b504aSStefan Roese		};
66667b504aSStefan Roese
67667b504aSStefan Roese		ethernet@3000 {
68667b504aSStefan Roese			phy-handle = <&phy0>;
69667b504aSStefan Roese		};
70667b504aSStefan Roese
71667b504aSStefan Roese		mdio@3000 {
72667b504aSStefan Roese			phy0: ethernet-phy@3 {
73667b504aSStefan Roese				reg = <0x03>;
74667b504aSStefan Roese			};
75667b504aSStefan Roese		};
76667b504aSStefan Roese
77667b504aSStefan Roese		ata@3a00 {
78667b504aSStefan Roese			status = "disabled";
79667b504aSStefan Roese		};
80667b504aSStefan Roese
81667b504aSStefan Roese		i2c@3d00 {
82667b504aSStefan Roese			status = "disabled";
83667b504aSStefan Roese		};
84667b504aSStefan Roese
85667b504aSStefan Roese		i2c@3d40 {
86667b504aSStefan Roese			status = "disabled";
87667b504aSStefan Roese		};
88667b504aSStefan Roese	};
89667b504aSStefan Roese
90667b504aSStefan Roese	localbus {
91667b504aSStefan Roese		compatible = "fsl,mpc5200b-lpb","simple-bus";
92667b504aSStefan Roese		#address-cells = <2>;
93667b504aSStefan Roese		#size-cells = <1>;
94667b504aSStefan Roese		ranges = <0 0 0xfc000000 0x02000000
95667b504aSStefan Roese			  3 0 0xe9000000 0x00080000
96667b504aSStefan Roese			  5 0 0xe8000000 0x00010000>;
97667b504aSStefan Roese
98667b504aSStefan Roese		flash@0,0 {
99667b504aSStefan Roese			#address-cells = <1>;
100667b504aSStefan Roese			#size-cells = <1>;
101667b504aSStefan Roese			reg = <0 0x0 0x02000000>;
102667b504aSStefan Roese			compatible = "cfi-flash";
103667b504aSStefan Roese			bank-width = <2>;
104600ecc19SMathieu Malaterre			partition@0 {
105667b504aSStefan Roese				label = "u-boot";
106667b504aSStefan Roese				reg = <0x00000000 0x00040000>;
107667b504aSStefan Roese				read-only;
108667b504aSStefan Roese			};
109600ecc19SMathieu Malaterre			partition@40000 {
110667b504aSStefan Roese				label = "env";
111667b504aSStefan Roese				reg = <0x00040000 0x00020000>;
112667b504aSStefan Roese			};
113600ecc19SMathieu Malaterre			partition@60000 {
114667b504aSStefan Roese				label = "dtb";
115667b504aSStefan Roese				reg = <0x00060000 0x00020000>;
116667b504aSStefan Roese			};
117600ecc19SMathieu Malaterre			partition@80000 {
118667b504aSStefan Roese				label = "kernel";
119667b504aSStefan Roese				reg = <0x00080000 0x00500000>;
120667b504aSStefan Roese			};
121600ecc19SMathieu Malaterre			partition@580000 {
122667b504aSStefan Roese				label = "root";
123667b504aSStefan Roese				reg = <0x00580000 0x00A80000>;
124667b504aSStefan Roese			};
125667b504aSStefan Roese		};
126667b504aSStefan Roese
127667b504aSStefan Roese		fpga@3,0 {
128667b504aSStefan Roese			compatible = "anonymous,a3m071-fpga";
129667b504aSStefan Roese			reg = <3 0x0 0x00080000
130667b504aSStefan Roese			       5 0x0 0x00010000>;
131667b504aSStefan Roese			interrupts = <0 0 3>;  /* level low */
132667b504aSStefan Roese		};
133667b504aSStefan Roese	};
134667b504aSStefan Roese
135667b504aSStefan Roese	pci@f0000d00 {
136667b504aSStefan Roese		status = "disabled";
137667b504aSStefan Roese	};
138667b504aSStefan Roese};
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