1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3/ { 4 compatible = "opencores,or1ksim"; 5 #address-cells = <1>; 6 #size-cells = <1>; 7 interrupt-parent = <&pic>; 8 9 chosen { 10 bootargs = "console=uart,mmio,0x90000000,115200"; 11 }; 12 13 memory@0 { 14 device_type = "memory"; 15 reg = <0x00000000 0x02000000>; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 cpu@0 { 22 compatible = "opencores,or1200-rtlsvn481"; 23 reg = <0>; 24 clock-frequency = <20000000>; 25 }; 26 }; 27 28 /* 29 * OR1K PIC is built into CPU and accessed via special purpose 30 * registers. It is not addressable and, hence, has no 'reg' 31 * property. 32 */ 33 pic: pic { 34 compatible = "opencores,or1k-pic"; 35 #interrupt-cells = <1>; 36 interrupt-controller; 37 }; 38 39 serial0: serial@90000000 { 40 compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; 41 reg = <0x90000000 0x100>; 42 interrupts = <2>; 43 clock-frequency = <20000000>; 44 }; 45 46 enet0: ethoc@92000000 { 47 compatible = "opencores,ethmac-rtlsvn338"; 48 reg = <0x92000000 0x100>; 49 interrupts = <4>; 50 }; 51}; 52