1/dts-v1/; 2/ { 3 compatible = "opencores,or1ksim"; 4 #address-cells = <1>; 5 #size-cells = <1>; 6 interrupt-parent = <&pic>; 7 8 aliases { 9 uart0 = &serial0; 10 }; 11 12 chosen { 13 bootargs = "earlycon"; 14 stdout-path = "uart0:115200"; 15 }; 16 17 memory@0 { 18 device_type = "memory"; 19 reg = <0x00000000 0x02000000>; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 cpu@0 { 26 compatible = "opencores,or1200-rtlsvn481"; 27 reg = <0>; 28 clock-frequency = <20000000>; 29 }; 30 }; 31 32 /* 33 * OR1K PIC is built into CPU and accessed via special purpose 34 * registers. It is not addressable and, hence, has no 'reg' 35 * property. 36 */ 37 pic: pic { 38 compatible = "opencores,or1k-pic"; 39 #interrupt-cells = <1>; 40 interrupt-controller; 41 }; 42 43 serial0: serial@90000000 { 44 compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; 45 reg = <0x90000000 0x100>; 46 interrupts = <2>; 47 clock-frequency = <20000000>; 48 }; 49 50 enet0: ethoc@92000000 { 51 compatible = "opencores,ethmac-rtlsvn338"; 52 reg = <0x92000000 0x100>; 53 interrupts = <4>; 54 }; 55}; 56