1/dts-v1/;
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/interrupt-controller/mips-gic.h>
5
6/memreserve/ 0x00000000 0x00001000;	/* YAMON exception vectors */
7/memreserve/ 0x00001000 0x000ef000;	/* YAMON */
8/memreserve/ 0x000f0000 0x00010000;	/* PIIX4 ISA memory */
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	compatible = "mti,malta";
14
15	cpu_intc: interrupt-controller {
16		compatible = "mti,cpu-interrupt-controller";
17
18		interrupt-controller;
19		#interrupt-cells = <1>;
20	};
21
22	gic: interrupt-controller@1bdc0000 {
23		compatible = "mti,gic";
24		reg = <0x1bdc0000 0x20000>;
25
26		interrupt-controller;
27		#interrupt-cells = <3>;
28
29		/*
30		 * Declare the interrupt-parent even though the mti,gic
31		 * binding doesn't require it, such that the kernel can
32		 * figure out that cpu_intc is the root interrupt
33		 * controller & should be probed first.
34		 */
35		interrupt-parent = <&cpu_intc>;
36
37		timer {
38			compatible = "mti,gic-timer";
39			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
40		};
41	};
42
43	i8259: interrupt-controller@20 {
44		compatible = "intel,i8259";
45
46		interrupt-controller;
47		#interrupt-cells = <1>;
48
49		interrupt-parent = <&gic>;
50		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
51	};
52
53	isa {
54		compatible = "isa";
55		#address-cells = <2>;
56		#size-cells = <1>;
57		ranges = <1 0 0 0x1000>;
58
59		rtc@70 {
60			compatible = "motorola,mc146818";
61			reg = <1 0x70 0x8>;
62
63			interrupt-parent = <&i8259>;
64			interrupts = <8>;
65		};
66	};
67};
68