1d843dd53SAlexandre Belloni// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d843dd53SAlexandre Belloni/* Copyright (c) 2017 Microsemi Corporation */ 3d843dd53SAlexandre Belloni 4d843dd53SAlexandre Belloni/ { 5d843dd53SAlexandre Belloni #address-cells = <1>; 6d843dd53SAlexandre Belloni #size-cells = <1>; 7d843dd53SAlexandre Belloni compatible = "mscc,ocelot"; 8d843dd53SAlexandre Belloni 9d843dd53SAlexandre Belloni cpus { 10d843dd53SAlexandre Belloni #address-cells = <1>; 11d843dd53SAlexandre Belloni #size-cells = <0>; 12d843dd53SAlexandre Belloni 13d843dd53SAlexandre Belloni cpu@0 { 14d843dd53SAlexandre Belloni compatible = "mips,mips24KEc"; 15d843dd53SAlexandre Belloni device_type = "cpu"; 16d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 17d843dd53SAlexandre Belloni reg = <0>; 18d843dd53SAlexandre Belloni }; 19d843dd53SAlexandre Belloni }; 20d843dd53SAlexandre Belloni 21d843dd53SAlexandre Belloni aliases { 22d843dd53SAlexandre Belloni serial0 = &uart0; 23d843dd53SAlexandre Belloni }; 24d843dd53SAlexandre Belloni 25d843dd53SAlexandre Belloni cpuintc: interrupt-controller { 26d843dd53SAlexandre Belloni #address-cells = <0>; 27d843dd53SAlexandre Belloni #interrupt-cells = <1>; 28d843dd53SAlexandre Belloni interrupt-controller; 29d843dd53SAlexandre Belloni compatible = "mti,cpu-interrupt-controller"; 30d843dd53SAlexandre Belloni }; 31d843dd53SAlexandre Belloni 32d843dd53SAlexandre Belloni cpu_clk: cpu-clock { 33d843dd53SAlexandre Belloni compatible = "fixed-clock"; 34d843dd53SAlexandre Belloni #clock-cells = <0>; 35d843dd53SAlexandre Belloni clock-frequency = <500000000>; 36d843dd53SAlexandre Belloni }; 37d843dd53SAlexandre Belloni 38d843dd53SAlexandre Belloni ahb_clk: ahb-clk { 39d843dd53SAlexandre Belloni compatible = "fixed-factor-clock"; 40d843dd53SAlexandre Belloni #clock-cells = <0>; 41d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 42d843dd53SAlexandre Belloni clock-div = <2>; 43d843dd53SAlexandre Belloni clock-mult = <1>; 44d843dd53SAlexandre Belloni }; 45d843dd53SAlexandre Belloni 46d843dd53SAlexandre Belloni ahb@70000000 { 47d843dd53SAlexandre Belloni compatible = "simple-bus"; 48d843dd53SAlexandre Belloni #address-cells = <1>; 49d843dd53SAlexandre Belloni #size-cells = <1>; 50d843dd53SAlexandre Belloni ranges = <0 0x70000000 0x2000000>; 51d843dd53SAlexandre Belloni 52d843dd53SAlexandre Belloni interrupt-parent = <&intc>; 53d843dd53SAlexandre Belloni 54d843dd53SAlexandre Belloni cpu_ctrl: syscon@0 { 55d843dd53SAlexandre Belloni compatible = "mscc,ocelot-cpu-syscon", "syscon"; 56d843dd53SAlexandre Belloni reg = <0x0 0x2c>; 57d843dd53SAlexandre Belloni }; 58d843dd53SAlexandre Belloni 59d843dd53SAlexandre Belloni intc: interrupt-controller@70 { 60d843dd53SAlexandre Belloni compatible = "mscc,ocelot-icpu-intr"; 61d843dd53SAlexandre Belloni reg = <0x70 0x70>; 62d843dd53SAlexandre Belloni #interrupt-cells = <1>; 63d843dd53SAlexandre Belloni interrupt-controller; 64d843dd53SAlexandre Belloni interrupt-parent = <&cpuintc>; 65d843dd53SAlexandre Belloni interrupts = <2>; 66d843dd53SAlexandre Belloni }; 67d843dd53SAlexandre Belloni 68d843dd53SAlexandre Belloni uart0: serial@100000 { 69d843dd53SAlexandre Belloni pinctrl-0 = <&uart_pins>; 70d843dd53SAlexandre Belloni pinctrl-names = "default"; 71d843dd53SAlexandre Belloni compatible = "ns16550a"; 72d843dd53SAlexandre Belloni reg = <0x100000 0x20>; 73d843dd53SAlexandre Belloni interrupts = <6>; 74d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 75d843dd53SAlexandre Belloni reg-io-width = <4>; 76d843dd53SAlexandre Belloni reg-shift = <2>; 77d843dd53SAlexandre Belloni 78d843dd53SAlexandre Belloni status = "disabled"; 79d843dd53SAlexandre Belloni }; 80d843dd53SAlexandre Belloni 81d843dd53SAlexandre Belloni uart2: serial@100800 { 82d843dd53SAlexandre Belloni pinctrl-0 = <&uart2_pins>; 83d843dd53SAlexandre Belloni pinctrl-names = "default"; 84d843dd53SAlexandre Belloni compatible = "ns16550a"; 85d843dd53SAlexandre Belloni reg = <0x100800 0x20>; 86d843dd53SAlexandre Belloni interrupts = <7>; 87d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 88d843dd53SAlexandre Belloni reg-io-width = <4>; 89d843dd53SAlexandre Belloni reg-shift = <2>; 90d843dd53SAlexandre Belloni 91d843dd53SAlexandre Belloni status = "disabled"; 92d843dd53SAlexandre Belloni }; 93d843dd53SAlexandre Belloni 94d843dd53SAlexandre Belloni reset@1070008 { 95d843dd53SAlexandre Belloni compatible = "mscc,ocelot-chip-reset"; 96d843dd53SAlexandre Belloni reg = <0x1070008 0x4>; 97d843dd53SAlexandre Belloni }; 98d843dd53SAlexandre Belloni 99d843dd53SAlexandre Belloni gpio: pinctrl@1070034 { 100d843dd53SAlexandre Belloni compatible = "mscc,ocelot-pinctrl"; 101d843dd53SAlexandre Belloni reg = <0x1070034 0x68>; 102d843dd53SAlexandre Belloni gpio-controller; 103d843dd53SAlexandre Belloni #gpio-cells = <2>; 104d843dd53SAlexandre Belloni gpio-ranges = <&gpio 0 0 22>; 105d843dd53SAlexandre Belloni 106d843dd53SAlexandre Belloni uart_pins: uart-pins { 107d843dd53SAlexandre Belloni pins = "GPIO_6", "GPIO_7"; 108d843dd53SAlexandre Belloni function = "uart"; 109d843dd53SAlexandre Belloni }; 110d843dd53SAlexandre Belloni 111d843dd53SAlexandre Belloni uart2_pins: uart2-pins { 112d843dd53SAlexandre Belloni pins = "GPIO_12", "GPIO_13"; 113d843dd53SAlexandre Belloni function = "uart2"; 114d843dd53SAlexandre Belloni }; 115d843dd53SAlexandre Belloni }; 116d843dd53SAlexandre Belloni }; 117d843dd53SAlexandre Belloni}; 118