1d843dd53SAlexandre Belloni// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d843dd53SAlexandre Belloni/* Copyright (c) 2017 Microsemi Corporation */ 3d843dd53SAlexandre Belloni 4d843dd53SAlexandre Belloni/ { 5d843dd53SAlexandre Belloni #address-cells = <1>; 6d843dd53SAlexandre Belloni #size-cells = <1>; 7d843dd53SAlexandre Belloni compatible = "mscc,ocelot"; 8d843dd53SAlexandre Belloni 9d843dd53SAlexandre Belloni cpus { 10d843dd53SAlexandre Belloni #address-cells = <1>; 11d843dd53SAlexandre Belloni #size-cells = <0>; 12d843dd53SAlexandre Belloni 13d843dd53SAlexandre Belloni cpu@0 { 14d843dd53SAlexandre Belloni compatible = "mips,mips24KEc"; 15d843dd53SAlexandre Belloni device_type = "cpu"; 16d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 17d843dd53SAlexandre Belloni reg = <0>; 18d843dd53SAlexandre Belloni }; 19d843dd53SAlexandre Belloni }; 20d843dd53SAlexandre Belloni 21d843dd53SAlexandre Belloni aliases { 22d843dd53SAlexandre Belloni serial0 = &uart0; 23d843dd53SAlexandre Belloni }; 24d843dd53SAlexandre Belloni 25d843dd53SAlexandre Belloni cpuintc: interrupt-controller { 26d843dd53SAlexandre Belloni #address-cells = <0>; 27d843dd53SAlexandre Belloni #interrupt-cells = <1>; 28d843dd53SAlexandre Belloni interrupt-controller; 29d843dd53SAlexandre Belloni compatible = "mti,cpu-interrupt-controller"; 30d843dd53SAlexandre Belloni }; 31d843dd53SAlexandre Belloni 32d843dd53SAlexandre Belloni cpu_clk: cpu-clock { 33d843dd53SAlexandre Belloni compatible = "fixed-clock"; 34d843dd53SAlexandre Belloni #clock-cells = <0>; 35d843dd53SAlexandre Belloni clock-frequency = <500000000>; 36d843dd53SAlexandre Belloni }; 37d843dd53SAlexandre Belloni 38d843dd53SAlexandre Belloni ahb_clk: ahb-clk { 39d843dd53SAlexandre Belloni compatible = "fixed-factor-clock"; 40d843dd53SAlexandre Belloni #clock-cells = <0>; 41d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 42d843dd53SAlexandre Belloni clock-div = <2>; 43d843dd53SAlexandre Belloni clock-mult = <1>; 44d843dd53SAlexandre Belloni }; 45d843dd53SAlexandre Belloni 46d843dd53SAlexandre Belloni ahb@70000000 { 47d843dd53SAlexandre Belloni compatible = "simple-bus"; 48d843dd53SAlexandre Belloni #address-cells = <1>; 49d843dd53SAlexandre Belloni #size-cells = <1>; 50d843dd53SAlexandre Belloni ranges = <0 0x70000000 0x2000000>; 51d843dd53SAlexandre Belloni 52d843dd53SAlexandre Belloni interrupt-parent = <&intc>; 53d843dd53SAlexandre Belloni 54d843dd53SAlexandre Belloni cpu_ctrl: syscon@0 { 55d843dd53SAlexandre Belloni compatible = "mscc,ocelot-cpu-syscon", "syscon"; 56d843dd53SAlexandre Belloni reg = <0x0 0x2c>; 57d843dd53SAlexandre Belloni }; 58d843dd53SAlexandre Belloni 59d843dd53SAlexandre Belloni intc: interrupt-controller@70 { 60d843dd53SAlexandre Belloni compatible = "mscc,ocelot-icpu-intr"; 61d843dd53SAlexandre Belloni reg = <0x70 0x70>; 62d843dd53SAlexandre Belloni #interrupt-cells = <1>; 63d843dd53SAlexandre Belloni interrupt-controller; 64d843dd53SAlexandre Belloni interrupt-parent = <&cpuintc>; 65d843dd53SAlexandre Belloni interrupts = <2>; 66d843dd53SAlexandre Belloni }; 67d843dd53SAlexandre Belloni 68d843dd53SAlexandre Belloni uart0: serial@100000 { 69d843dd53SAlexandre Belloni pinctrl-0 = <&uart_pins>; 70d843dd53SAlexandre Belloni pinctrl-names = "default"; 71d843dd53SAlexandre Belloni compatible = "ns16550a"; 72d843dd53SAlexandre Belloni reg = <0x100000 0x20>; 73d843dd53SAlexandre Belloni interrupts = <6>; 74d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 75d843dd53SAlexandre Belloni reg-io-width = <4>; 76d843dd53SAlexandre Belloni reg-shift = <2>; 77d843dd53SAlexandre Belloni 78d843dd53SAlexandre Belloni status = "disabled"; 79d843dd53SAlexandre Belloni }; 80d843dd53SAlexandre Belloni 81d843dd53SAlexandre Belloni uart2: serial@100800 { 82d843dd53SAlexandre Belloni pinctrl-0 = <&uart2_pins>; 83d843dd53SAlexandre Belloni pinctrl-names = "default"; 84d843dd53SAlexandre Belloni compatible = "ns16550a"; 85d843dd53SAlexandre Belloni reg = <0x100800 0x20>; 86d843dd53SAlexandre Belloni interrupts = <7>; 87d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 88d843dd53SAlexandre Belloni reg-io-width = <4>; 89d843dd53SAlexandre Belloni reg-shift = <2>; 90d843dd53SAlexandre Belloni 91d843dd53SAlexandre Belloni status = "disabled"; 92d843dd53SAlexandre Belloni }; 93d843dd53SAlexandre Belloni 949eaf3ba5SAlexandre Belloni spi: spi@101000 { 959eaf3ba5SAlexandre Belloni compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; 969eaf3ba5SAlexandre Belloni #address-cells = <1>; 979eaf3ba5SAlexandre Belloni #size-cells = <0>; 989eaf3ba5SAlexandre Belloni reg = <0x101000 0x100>, <0x3c 0x18>; 999eaf3ba5SAlexandre Belloni interrupts = <9>; 1009eaf3ba5SAlexandre Belloni clocks = <&ahb_clk>; 1019eaf3ba5SAlexandre Belloni 1029eaf3ba5SAlexandre Belloni status = "disabled"; 1039eaf3ba5SAlexandre Belloni }; 1049eaf3ba5SAlexandre Belloni 10549b03169SAlexandre Belloni switch@1010000 { 10649b03169SAlexandre Belloni compatible = "mscc,vsc7514-switch"; 10749b03169SAlexandre Belloni reg = <0x1010000 0x10000>, 10849b03169SAlexandre Belloni <0x1030000 0x10000>, 10949b03169SAlexandre Belloni <0x1080000 0x100>, 11049b03169SAlexandre Belloni <0x10d0000 0x10000>, 11149b03169SAlexandre Belloni <0x11e0000 0x100>, 11249b03169SAlexandre Belloni <0x11f0000 0x100>, 11349b03169SAlexandre Belloni <0x1200000 0x100>, 11449b03169SAlexandre Belloni <0x1210000 0x100>, 11549b03169SAlexandre Belloni <0x1220000 0x100>, 11649b03169SAlexandre Belloni <0x1230000 0x100>, 11749b03169SAlexandre Belloni <0x1240000 0x100>, 11849b03169SAlexandre Belloni <0x1250000 0x100>, 11949b03169SAlexandre Belloni <0x1260000 0x100>, 12049b03169SAlexandre Belloni <0x1270000 0x100>, 12149b03169SAlexandre Belloni <0x1280000 0x100>, 12249b03169SAlexandre Belloni <0x1800000 0x80000>, 12349b03169SAlexandre Belloni <0x1880000 0x10000>; 12449b03169SAlexandre Belloni reg-names = "sys", "rew", "qs", "hsio", "port0", 12549b03169SAlexandre Belloni "port1", "port2", "port3", "port4", "port5", 12649b03169SAlexandre Belloni "port6", "port7", "port8", "port9", "port10", 12749b03169SAlexandre Belloni "qsys", "ana"; 12849b03169SAlexandre Belloni interrupts = <21 22>; 12949b03169SAlexandre Belloni interrupt-names = "xtr", "inj"; 13049b03169SAlexandre Belloni 13149b03169SAlexandre Belloni ethernet-ports { 13249b03169SAlexandre Belloni #address-cells = <1>; 13349b03169SAlexandre Belloni #size-cells = <0>; 13449b03169SAlexandre Belloni 13549b03169SAlexandre Belloni port0: port@0 { 13649b03169SAlexandre Belloni reg = <0>; 13749b03169SAlexandre Belloni }; 13849b03169SAlexandre Belloni port1: port@1 { 13949b03169SAlexandre Belloni reg = <1>; 14049b03169SAlexandre Belloni }; 14149b03169SAlexandre Belloni port2: port@2 { 14249b03169SAlexandre Belloni reg = <2>; 14349b03169SAlexandre Belloni }; 14449b03169SAlexandre Belloni port3: port@3 { 14549b03169SAlexandre Belloni reg = <3>; 14649b03169SAlexandre Belloni }; 14749b03169SAlexandre Belloni port4: port@4 { 14849b03169SAlexandre Belloni reg = <4>; 14949b03169SAlexandre Belloni }; 15049b03169SAlexandre Belloni port5: port@5 { 15149b03169SAlexandre Belloni reg = <5>; 15249b03169SAlexandre Belloni }; 15349b03169SAlexandre Belloni port6: port@6 { 15449b03169SAlexandre Belloni reg = <6>; 15549b03169SAlexandre Belloni }; 15649b03169SAlexandre Belloni port7: port@7 { 15749b03169SAlexandre Belloni reg = <7>; 15849b03169SAlexandre Belloni }; 15949b03169SAlexandre Belloni port8: port@8 { 16049b03169SAlexandre Belloni reg = <8>; 16149b03169SAlexandre Belloni }; 16249b03169SAlexandre Belloni port9: port@9 { 16349b03169SAlexandre Belloni reg = <9>; 16449b03169SAlexandre Belloni }; 16549b03169SAlexandre Belloni port10: port@10 { 16649b03169SAlexandre Belloni reg = <10>; 16749b03169SAlexandre Belloni }; 16849b03169SAlexandre Belloni }; 16949b03169SAlexandre Belloni }; 17049b03169SAlexandre Belloni 171d843dd53SAlexandre Belloni reset@1070008 { 172d843dd53SAlexandre Belloni compatible = "mscc,ocelot-chip-reset"; 173d843dd53SAlexandre Belloni reg = <0x1070008 0x4>; 174d843dd53SAlexandre Belloni }; 175d843dd53SAlexandre Belloni 176d843dd53SAlexandre Belloni gpio: pinctrl@1070034 { 177d843dd53SAlexandre Belloni compatible = "mscc,ocelot-pinctrl"; 178d843dd53SAlexandre Belloni reg = <0x1070034 0x68>; 179d843dd53SAlexandre Belloni gpio-controller; 180d843dd53SAlexandre Belloni #gpio-cells = <2>; 181d843dd53SAlexandre Belloni gpio-ranges = <&gpio 0 0 22>; 1826386889aSQuentin Schulz interrupt-controller; 1836386889aSQuentin Schulz interrupts = <13>; 1846386889aSQuentin Schulz #interrupt-cells = <2>; 185d843dd53SAlexandre Belloni 186d843dd53SAlexandre Belloni uart_pins: uart-pins { 187d843dd53SAlexandre Belloni pins = "GPIO_6", "GPIO_7"; 188d843dd53SAlexandre Belloni function = "uart"; 189d843dd53SAlexandre Belloni }; 190d843dd53SAlexandre Belloni 191d843dd53SAlexandre Belloni uart2_pins: uart2-pins { 192d843dd53SAlexandre Belloni pins = "GPIO_12", "GPIO_13"; 193d843dd53SAlexandre Belloni function = "uart2"; 194d843dd53SAlexandre Belloni }; 195a0553e01SQuentin Schulz 196a0553e01SQuentin Schulz miim1: miim1 { 197a0553e01SQuentin Schulz pins = "GPIO_14", "GPIO_15"; 198a0553e01SQuentin Schulz function = "miim1"; 199a0553e01SQuentin Schulz }; 200d843dd53SAlexandre Belloni }; 20149b03169SAlexandre Belloni 20249b03169SAlexandre Belloni mdio0: mdio@107009c { 20349b03169SAlexandre Belloni #address-cells = <1>; 20449b03169SAlexandre Belloni #size-cells = <0>; 20549b03169SAlexandre Belloni compatible = "mscc,ocelot-miim"; 20649e5bb13SQuentin Schulz reg = <0x107009c 0x24>, <0x10700f0 0x8>; 20749b03169SAlexandre Belloni interrupts = <14>; 20849b03169SAlexandre Belloni status = "disabled"; 20949b03169SAlexandre Belloni 21049b03169SAlexandre Belloni phy0: ethernet-phy@0 { 21149b03169SAlexandre Belloni reg = <0>; 21249b03169SAlexandre Belloni }; 21349b03169SAlexandre Belloni phy1: ethernet-phy@1 { 21449b03169SAlexandre Belloni reg = <1>; 21549b03169SAlexandre Belloni }; 21649b03169SAlexandre Belloni phy2: ethernet-phy@2 { 21749b03169SAlexandre Belloni reg = <2>; 21849b03169SAlexandre Belloni }; 21949b03169SAlexandre Belloni phy3: ethernet-phy@3 { 22049b03169SAlexandre Belloni reg = <3>; 22149b03169SAlexandre Belloni }; 22249b03169SAlexandre Belloni }; 223a0553e01SQuentin Schulz 224a0553e01SQuentin Schulz mdio1: mdio@10700c0 { 225a0553e01SQuentin Schulz #address-cells = <1>; 226a0553e01SQuentin Schulz #size-cells = <0>; 227a0553e01SQuentin Schulz compatible = "mscc,ocelot-miim"; 228a0553e01SQuentin Schulz reg = <0x10700c0 0x24>; 229a0553e01SQuentin Schulz interrupts = <15>; 230a0553e01SQuentin Schulz pinctrl-names = "default"; 231a0553e01SQuentin Schulz pinctrl-0 = <&miim1>; 232a0553e01SQuentin Schulz status = "disabled"; 233a0553e01SQuentin Schulz }; 234d843dd53SAlexandre Belloni }; 235d843dd53SAlexandre Belloni}; 236