1d843dd53SAlexandre Belloni// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d843dd53SAlexandre Belloni/* Copyright (c) 2017 Microsemi Corporation */ 3d843dd53SAlexandre Belloni 4d843dd53SAlexandre Belloni/ { 5d843dd53SAlexandre Belloni #address-cells = <1>; 6d843dd53SAlexandre Belloni #size-cells = <1>; 7d843dd53SAlexandre Belloni compatible = "mscc,ocelot"; 8d843dd53SAlexandre Belloni 9d843dd53SAlexandre Belloni cpus { 10d843dd53SAlexandre Belloni #address-cells = <1>; 11d843dd53SAlexandre Belloni #size-cells = <0>; 12d843dd53SAlexandre Belloni 13d843dd53SAlexandre Belloni cpu@0 { 14d843dd53SAlexandre Belloni compatible = "mips,mips24KEc"; 15d843dd53SAlexandre Belloni device_type = "cpu"; 16d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 17d843dd53SAlexandre Belloni reg = <0>; 18d843dd53SAlexandre Belloni }; 19d843dd53SAlexandre Belloni }; 20d843dd53SAlexandre Belloni 21d843dd53SAlexandre Belloni aliases { 22d843dd53SAlexandre Belloni serial0 = &uart0; 23d843dd53SAlexandre Belloni }; 24d843dd53SAlexandre Belloni 25d843dd53SAlexandre Belloni cpuintc: interrupt-controller { 26d843dd53SAlexandre Belloni #address-cells = <0>; 27d843dd53SAlexandre Belloni #interrupt-cells = <1>; 28d843dd53SAlexandre Belloni interrupt-controller; 29d843dd53SAlexandre Belloni compatible = "mti,cpu-interrupt-controller"; 30d843dd53SAlexandre Belloni }; 31d843dd53SAlexandre Belloni 32d843dd53SAlexandre Belloni cpu_clk: cpu-clock { 33d843dd53SAlexandre Belloni compatible = "fixed-clock"; 34d843dd53SAlexandre Belloni #clock-cells = <0>; 35d843dd53SAlexandre Belloni clock-frequency = <500000000>; 36d843dd53SAlexandre Belloni }; 37d843dd53SAlexandre Belloni 38d843dd53SAlexandre Belloni ahb_clk: ahb-clk { 39d843dd53SAlexandre Belloni compatible = "fixed-factor-clock"; 40d843dd53SAlexandre Belloni #clock-cells = <0>; 41d843dd53SAlexandre Belloni clocks = <&cpu_clk>; 42d843dd53SAlexandre Belloni clock-div = <2>; 43d843dd53SAlexandre Belloni clock-mult = <1>; 44d843dd53SAlexandre Belloni }; 45d843dd53SAlexandre Belloni 46d843dd53SAlexandre Belloni ahb@70000000 { 47d843dd53SAlexandre Belloni compatible = "simple-bus"; 48d843dd53SAlexandre Belloni #address-cells = <1>; 49d843dd53SAlexandre Belloni #size-cells = <1>; 50d843dd53SAlexandre Belloni ranges = <0 0x70000000 0x2000000>; 51d843dd53SAlexandre Belloni 52d843dd53SAlexandre Belloni interrupt-parent = <&intc>; 53d843dd53SAlexandre Belloni 54d843dd53SAlexandre Belloni cpu_ctrl: syscon@0 { 55d843dd53SAlexandre Belloni compatible = "mscc,ocelot-cpu-syscon", "syscon"; 56d843dd53SAlexandre Belloni reg = <0x0 0x2c>; 57d843dd53SAlexandre Belloni }; 58d843dd53SAlexandre Belloni 59d843dd53SAlexandre Belloni intc: interrupt-controller@70 { 60d843dd53SAlexandre Belloni compatible = "mscc,ocelot-icpu-intr"; 61d843dd53SAlexandre Belloni reg = <0x70 0x70>; 62d843dd53SAlexandre Belloni #interrupt-cells = <1>; 63d843dd53SAlexandre Belloni interrupt-controller; 64d843dd53SAlexandre Belloni interrupt-parent = <&cpuintc>; 65d843dd53SAlexandre Belloni interrupts = <2>; 66d843dd53SAlexandre Belloni }; 67d843dd53SAlexandre Belloni 68d843dd53SAlexandre Belloni uart0: serial@100000 { 69d843dd53SAlexandre Belloni pinctrl-0 = <&uart_pins>; 70d843dd53SAlexandre Belloni pinctrl-names = "default"; 71d843dd53SAlexandre Belloni compatible = "ns16550a"; 72d843dd53SAlexandre Belloni reg = <0x100000 0x20>; 73d843dd53SAlexandre Belloni interrupts = <6>; 74d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 75d843dd53SAlexandre Belloni reg-io-width = <4>; 76d843dd53SAlexandre Belloni reg-shift = <2>; 77d843dd53SAlexandre Belloni 78d843dd53SAlexandre Belloni status = "disabled"; 79d843dd53SAlexandre Belloni }; 80d843dd53SAlexandre Belloni 819ca953a3SAlexandre Belloni i2c: i2c@100400 { 829ca953a3SAlexandre Belloni compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; 839ca953a3SAlexandre Belloni pinctrl-0 = <&i2c_pins>; 849ca953a3SAlexandre Belloni pinctrl-names = "default"; 859ca953a3SAlexandre Belloni reg = <0x100400 0x100>, <0x198 0x8>; 869ca953a3SAlexandre Belloni #address-cells = <1>; 879ca953a3SAlexandre Belloni #size-cells = <0>; 889ca953a3SAlexandre Belloni interrupts = <8>; 899ca953a3SAlexandre Belloni clocks = <&ahb_clk>; 909ca953a3SAlexandre Belloni 919ca953a3SAlexandre Belloni status = "disabled"; 929ca953a3SAlexandre Belloni }; 939ca953a3SAlexandre Belloni 94d843dd53SAlexandre Belloni uart2: serial@100800 { 95d843dd53SAlexandre Belloni pinctrl-0 = <&uart2_pins>; 96d843dd53SAlexandre Belloni pinctrl-names = "default"; 97d843dd53SAlexandre Belloni compatible = "ns16550a"; 98d843dd53SAlexandre Belloni reg = <0x100800 0x20>; 99d843dd53SAlexandre Belloni interrupts = <7>; 100d843dd53SAlexandre Belloni clocks = <&ahb_clk>; 101d843dd53SAlexandre Belloni reg-io-width = <4>; 102d843dd53SAlexandre Belloni reg-shift = <2>; 103d843dd53SAlexandre Belloni 104d843dd53SAlexandre Belloni status = "disabled"; 105d843dd53SAlexandre Belloni }; 106d843dd53SAlexandre Belloni 1079eaf3ba5SAlexandre Belloni spi: spi@101000 { 1089eaf3ba5SAlexandre Belloni compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; 1099eaf3ba5SAlexandre Belloni #address-cells = <1>; 1109eaf3ba5SAlexandre Belloni #size-cells = <0>; 1119eaf3ba5SAlexandre Belloni reg = <0x101000 0x100>, <0x3c 0x18>; 1129eaf3ba5SAlexandre Belloni interrupts = <9>; 1139eaf3ba5SAlexandre Belloni clocks = <&ahb_clk>; 1149eaf3ba5SAlexandre Belloni 1159eaf3ba5SAlexandre Belloni status = "disabled"; 1169eaf3ba5SAlexandre Belloni }; 1179eaf3ba5SAlexandre Belloni 11849b03169SAlexandre Belloni switch@1010000 { 11949b03169SAlexandre Belloni compatible = "mscc,vsc7514-switch"; 12049b03169SAlexandre Belloni reg = <0x1010000 0x10000>, 12149b03169SAlexandre Belloni <0x1030000 0x10000>, 12249b03169SAlexandre Belloni <0x1080000 0x100>, 12349b03169SAlexandre Belloni <0x10d0000 0x10000>, 12449b03169SAlexandre Belloni <0x11e0000 0x100>, 12549b03169SAlexandre Belloni <0x11f0000 0x100>, 12649b03169SAlexandre Belloni <0x1200000 0x100>, 12749b03169SAlexandre Belloni <0x1210000 0x100>, 12849b03169SAlexandre Belloni <0x1220000 0x100>, 12949b03169SAlexandre Belloni <0x1230000 0x100>, 13049b03169SAlexandre Belloni <0x1240000 0x100>, 13149b03169SAlexandre Belloni <0x1250000 0x100>, 13249b03169SAlexandre Belloni <0x1260000 0x100>, 13349b03169SAlexandre Belloni <0x1270000 0x100>, 13449b03169SAlexandre Belloni <0x1280000 0x100>, 13549b03169SAlexandre Belloni <0x1800000 0x80000>, 13649b03169SAlexandre Belloni <0x1880000 0x10000>; 13749b03169SAlexandre Belloni reg-names = "sys", "rew", "qs", "hsio", "port0", 13849b03169SAlexandre Belloni "port1", "port2", "port3", "port4", "port5", 13949b03169SAlexandre Belloni "port6", "port7", "port8", "port9", "port10", 14049b03169SAlexandre Belloni "qsys", "ana"; 14149b03169SAlexandre Belloni interrupts = <21 22>; 14249b03169SAlexandre Belloni interrupt-names = "xtr", "inj"; 14349b03169SAlexandre Belloni 14449b03169SAlexandre Belloni ethernet-ports { 14549b03169SAlexandre Belloni #address-cells = <1>; 14649b03169SAlexandre Belloni #size-cells = <0>; 14749b03169SAlexandre Belloni 14849b03169SAlexandre Belloni port0: port@0 { 14949b03169SAlexandre Belloni reg = <0>; 15049b03169SAlexandre Belloni }; 15149b03169SAlexandre Belloni port1: port@1 { 15249b03169SAlexandre Belloni reg = <1>; 15349b03169SAlexandre Belloni }; 15449b03169SAlexandre Belloni port2: port@2 { 15549b03169SAlexandre Belloni reg = <2>; 15649b03169SAlexandre Belloni }; 15749b03169SAlexandre Belloni port3: port@3 { 15849b03169SAlexandre Belloni reg = <3>; 15949b03169SAlexandre Belloni }; 16049b03169SAlexandre Belloni port4: port@4 { 16149b03169SAlexandre Belloni reg = <4>; 16249b03169SAlexandre Belloni }; 16349b03169SAlexandre Belloni port5: port@5 { 16449b03169SAlexandre Belloni reg = <5>; 16549b03169SAlexandre Belloni }; 16649b03169SAlexandre Belloni port6: port@6 { 16749b03169SAlexandre Belloni reg = <6>; 16849b03169SAlexandre Belloni }; 16949b03169SAlexandre Belloni port7: port@7 { 17049b03169SAlexandre Belloni reg = <7>; 17149b03169SAlexandre Belloni }; 17249b03169SAlexandre Belloni port8: port@8 { 17349b03169SAlexandre Belloni reg = <8>; 17449b03169SAlexandre Belloni }; 17549b03169SAlexandre Belloni port9: port@9 { 17649b03169SAlexandre Belloni reg = <9>; 17749b03169SAlexandre Belloni }; 17849b03169SAlexandre Belloni port10: port@10 { 17949b03169SAlexandre Belloni reg = <10>; 18049b03169SAlexandre Belloni }; 18149b03169SAlexandre Belloni }; 18249b03169SAlexandre Belloni }; 18349b03169SAlexandre Belloni 184d843dd53SAlexandre Belloni reset@1070008 { 185d843dd53SAlexandre Belloni compatible = "mscc,ocelot-chip-reset"; 186d843dd53SAlexandre Belloni reg = <0x1070008 0x4>; 187d843dd53SAlexandre Belloni }; 188d843dd53SAlexandre Belloni 189d843dd53SAlexandre Belloni gpio: pinctrl@1070034 { 190d843dd53SAlexandre Belloni compatible = "mscc,ocelot-pinctrl"; 191d843dd53SAlexandre Belloni reg = <0x1070034 0x68>; 192d843dd53SAlexandre Belloni gpio-controller; 193d843dd53SAlexandre Belloni #gpio-cells = <2>; 194d843dd53SAlexandre Belloni gpio-ranges = <&gpio 0 0 22>; 1956386889aSQuentin Schulz interrupt-controller; 1966386889aSQuentin Schulz interrupts = <13>; 1976386889aSQuentin Schulz #interrupt-cells = <2>; 198d843dd53SAlexandre Belloni 1999ca953a3SAlexandre Belloni i2c_pins: i2c-pins { 2009ca953a3SAlexandre Belloni pins = "GPIO_16", "GPIO_17"; 2019ca953a3SAlexandre Belloni function = "twi"; 2029ca953a3SAlexandre Belloni }; 2039ca953a3SAlexandre Belloni 204d843dd53SAlexandre Belloni uart_pins: uart-pins { 205d843dd53SAlexandre Belloni pins = "GPIO_6", "GPIO_7"; 206d843dd53SAlexandre Belloni function = "uart"; 207d843dd53SAlexandre Belloni }; 208d843dd53SAlexandre Belloni 209d843dd53SAlexandre Belloni uart2_pins: uart2-pins { 210d843dd53SAlexandre Belloni pins = "GPIO_12", "GPIO_13"; 211d843dd53SAlexandre Belloni function = "uart2"; 212d843dd53SAlexandre Belloni }; 213a0553e01SQuentin Schulz 214a0553e01SQuentin Schulz miim1: miim1 { 215a0553e01SQuentin Schulz pins = "GPIO_14", "GPIO_15"; 216a0553e01SQuentin Schulz function = "miim1"; 217a0553e01SQuentin Schulz }; 2189ca953a3SAlexandre Belloni 219d843dd53SAlexandre Belloni }; 22049b03169SAlexandre Belloni 22149b03169SAlexandre Belloni mdio0: mdio@107009c { 22249b03169SAlexandre Belloni #address-cells = <1>; 22349b03169SAlexandre Belloni #size-cells = <0>; 22449b03169SAlexandre Belloni compatible = "mscc,ocelot-miim"; 22549e5bb13SQuentin Schulz reg = <0x107009c 0x24>, <0x10700f0 0x8>; 22649b03169SAlexandre Belloni interrupts = <14>; 22749b03169SAlexandre Belloni status = "disabled"; 22849b03169SAlexandre Belloni 22949b03169SAlexandre Belloni phy0: ethernet-phy@0 { 23049b03169SAlexandre Belloni reg = <0>; 23149b03169SAlexandre Belloni }; 23249b03169SAlexandre Belloni phy1: ethernet-phy@1 { 23349b03169SAlexandre Belloni reg = <1>; 23449b03169SAlexandre Belloni }; 23549b03169SAlexandre Belloni phy2: ethernet-phy@2 { 23649b03169SAlexandre Belloni reg = <2>; 23749b03169SAlexandre Belloni }; 23849b03169SAlexandre Belloni phy3: ethernet-phy@3 { 23949b03169SAlexandre Belloni reg = <3>; 24049b03169SAlexandre Belloni }; 24149b03169SAlexandre Belloni }; 242a0553e01SQuentin Schulz 243a0553e01SQuentin Schulz mdio1: mdio@10700c0 { 244a0553e01SQuentin Schulz #address-cells = <1>; 245a0553e01SQuentin Schulz #size-cells = <0>; 246a0553e01SQuentin Schulz compatible = "mscc,ocelot-miim"; 247a0553e01SQuentin Schulz reg = <0x10700c0 0x24>; 248a0553e01SQuentin Schulz interrupts = <15>; 249a0553e01SQuentin Schulz pinctrl-names = "default"; 250a0553e01SQuentin Schulz pinctrl-0 = <&miim1>; 251a0553e01SQuentin Schulz status = "disabled"; 252a0553e01SQuentin Schulz }; 253d843dd53SAlexandre Belloni }; 254d843dd53SAlexandre Belloni}; 255