13e4d618bSGabriel Fernandez /* 23e4d618bSGabriel Fernandez * This header provides constants for the STM32H7 RCC IP 33e4d618bSGabriel Fernandez */ 43e4d618bSGabriel Fernandez 53e4d618bSGabriel Fernandez #ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H 63e4d618bSGabriel Fernandez #define _DT_BINDINGS_MFD_STM32H7_RCC_H 73e4d618bSGabriel Fernandez 83e4d618bSGabriel Fernandez /* AHB3 */ 93e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_MDMA 0 103e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_DMA2D 4 113e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_JPGDEC 5 123e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_FMC 12 133e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_QUADSPI 14 143e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_SDMMC1 16 153e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB3_CPU 31 163e4d618bSGabriel Fernandez 173e4d618bSGabriel Fernandez #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) 183e4d618bSGabriel Fernandez 193e4d618bSGabriel Fernandez /* AHB1 */ 203e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_DMA1 0 213e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_DMA2 1 223e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_ADC12 5 233e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_ART 14 243e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_ETH1MAC 15 253e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_USB1OTG 25 263e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB1_USB2OTG 27 273e4d618bSGabriel Fernandez 283e4d618bSGabriel Fernandez #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) 293e4d618bSGabriel Fernandez 303e4d618bSGabriel Fernandez /* AHB2 */ 313e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB2_CAMITF 0 323e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB2_CRYPT 4 333e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB2_HASH 5 343e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB2_RNG 6 353e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB2_SDMMC2 9 363e4d618bSGabriel Fernandez 373e4d618bSGabriel Fernandez #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) 383e4d618bSGabriel Fernandez 393e4d618bSGabriel Fernandez /* AHB4 */ 403e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOA 0 413e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOB 1 423e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOC 2 433e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOD 3 443e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOE 4 453e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOF 5 463e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOG 6 473e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOH 7 483e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOI 8 493e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOJ 9 503e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_GPIOK 10 513e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_CRC 19 523e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_BDMA 21 533e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_ADC3 24 543e4d618bSGabriel Fernandez #define STM32H7_RCC_AHB4_HSEM 25 553e4d618bSGabriel Fernandez 563e4d618bSGabriel Fernandez #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) 573e4d618bSGabriel Fernandez 583e4d618bSGabriel Fernandez /* APB3 */ 593e4d618bSGabriel Fernandez #define STM32H7_RCC_APB3_LTDC 3 603e4d618bSGabriel Fernandez #define STM32H7_RCC_APB3_DSI 4 613e4d618bSGabriel Fernandez 623e4d618bSGabriel Fernandez #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) 633e4d618bSGabriel Fernandez 643e4d618bSGabriel Fernandez /* APB1L */ 653e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM2 0 663e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM3 1 673e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM4 2 683e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM5 3 693e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM6 4 703e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM7 5 713e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM12 6 723e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM13 7 733e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_TIM14 8 743e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_LPTIM1 9 753e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_SPI2 14 763e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_SPI3 15 773e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_SPDIF_RX 16 783e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_USART2 17 793e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_USART3 18 803e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_UART4 19 813e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_UART5 20 823e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_I2C1 21 833e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_I2C2 22 843e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_I2C3 23 853e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_HDMICEC 27 863e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_DAC12 29 873e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_USART7 30 883e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1L_USART8 31 893e4d618bSGabriel Fernandez 903e4d618bSGabriel Fernandez #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) 913e4d618bSGabriel Fernandez 923e4d618bSGabriel Fernandez /* APB1H */ 933e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1H_CRS 1 943e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1H_SWP 2 953e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1H_OPAMP 4 963e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1H_MDIOS 5 973e4d618bSGabriel Fernandez #define STM32H7_RCC_APB1H_FDCAN 8 983e4d618bSGabriel Fernandez 993e4d618bSGabriel Fernandez #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) 1003e4d618bSGabriel Fernandez 1013e4d618bSGabriel Fernandez /* APB2 */ 1023e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_TIM1 0 1033e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_TIM8 1 1043e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_USART1 4 1053e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_USART6 5 1063e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SPI1 12 1073e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SPI4 13 1083e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_TIM15 16 1093e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_TIM16 17 1103e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_TIM17 18 1113e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SPI5 20 1123e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SAI1 22 1133e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SAI2 23 1143e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_SAI3 24 1153e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_DFSDM1 28 1163e4d618bSGabriel Fernandez #define STM32H7_RCC_APB2_HRTIM 29 1173e4d618bSGabriel Fernandez 1183e4d618bSGabriel Fernandez #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) 1193e4d618bSGabriel Fernandez 1203e4d618bSGabriel Fernandez /* APB4 */ 1213e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_SYSCFG 1 1223e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_LPUART1 3 1233e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_SPI6 5 1243e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_I2C4 7 1253e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_LPTIM2 9 1263e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_LPTIM3 10 1273e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_LPTIM4 11 1283e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_LPTIM5 12 1293e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_COMP12 14 1303e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_VREF 15 1313e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_SAI4 21 1323e4d618bSGabriel Fernandez #define STM32H7_RCC_APB4_TMPSENS 26 1333e4d618bSGabriel Fernandez 1343e4d618bSGabriel Fernandez #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) 1353e4d618bSGabriel Fernandez 1363e4d618bSGabriel Fernandez #endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ 137