1156fdf11SGabriel Fernandez /* 2156fdf11SGabriel Fernandez * This header provides constants for the STM32F7 RCC IP 3156fdf11SGabriel Fernandez */ 4156fdf11SGabriel Fernandez 5156fdf11SGabriel Fernandez #ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H 6156fdf11SGabriel Fernandez #define _DT_BINDINGS_MFD_STM32F7_RCC_H 7156fdf11SGabriel Fernandez 8156fdf11SGabriel Fernandez /* AHB1 */ 9156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOA 0 10156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOB 1 11156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOC 2 12156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOD 3 13156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOE 4 14156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOF 5 15156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOG 6 16156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOH 7 17156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOI 8 18156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOJ 9 19156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOK 10 20156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_CRC 12 21156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_BKPSRAM 18 22156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DTCMRAM 20 23156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA1 21 24156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA2 22 25156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA2D 23 26156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMAC 25 27156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMACTX 26 28156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMACRX 27 29156fdf11SGabriel Fernandez #define STM32FF_RCC_AHB1_ETHMACPTP 28 30156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_OTGHS 29 31156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_OTGHSULPI 30 32156fdf11SGabriel Fernandez 33156fdf11SGabriel Fernandez #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) 34156fdf11SGabriel Fernandez #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) 35156fdf11SGabriel Fernandez 36156fdf11SGabriel Fernandez 37156fdf11SGabriel Fernandez /* AHB2 */ 38156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_DCMI 0 39156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_CRYP 4 40156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_HASH 5 41156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_RNG 6 42156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_OTGFS 7 43156fdf11SGabriel Fernandez 44156fdf11SGabriel Fernandez #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) 45156fdf11SGabriel Fernandez #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) 46156fdf11SGabriel Fernandez 47156fdf11SGabriel Fernandez /* AHB3 */ 48156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB3_FMC 0 49156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB3_QSPI 1 50156fdf11SGabriel Fernandez 51156fdf11SGabriel Fernandez #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) 52156fdf11SGabriel Fernandez #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) 53156fdf11SGabriel Fernandez 54156fdf11SGabriel Fernandez /* APB1 */ 55156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM2 0 56156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM3 1 57156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM4 2 58156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM5 3 59156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM6 4 60156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM7 5 61156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM12 6 62156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM13 7 63156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM14 8 64156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_LPTIM1 9 65156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_WWDG 11 66156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPI2 14 67156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPI3 15 68156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPDIFRX 16 69156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART2 17 70156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART3 18 71156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART4 19 72156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART5 20 73156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C1 21 74156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C2 22 75156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C3 23 76156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C4 24 77156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CAN1 25 78156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CAN2 26 79156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CEC 27 80156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_PWR 28 81156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_DAC 29 82156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART7 30 83156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART8 31 84156fdf11SGabriel Fernandez 85156fdf11SGabriel Fernandez #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) 86156fdf11SGabriel Fernandez #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) 87156fdf11SGabriel Fernandez 88156fdf11SGabriel Fernandez /* APB2 */ 89156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM1 0 90156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM8 1 91156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_USART1 4 92156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_USART6 5 93156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC1 8 94156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC2 9 95156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC3 10 96156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SDMMC1 11 97156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI1 12 98156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI4 13 99156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SYSCFG 14 100156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM9 16 101156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM10 17 102156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM11 18 103156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI5 20 104156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI6 21 105156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SAI1 22 106156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SAI2 23 107156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_LTDC 26 108156fdf11SGabriel Fernandez 109156fdf11SGabriel Fernandez #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) 110156fdf11SGabriel Fernandez #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) 111156fdf11SGabriel Fernandez 112156fdf11SGabriel Fernandez #endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ 113