1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2156fdf11SGabriel Fernandez /* 3156fdf11SGabriel Fernandez * This header provides constants for the STM32F7 RCC IP 4156fdf11SGabriel Fernandez */ 5156fdf11SGabriel Fernandez 6156fdf11SGabriel Fernandez #ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H 7156fdf11SGabriel Fernandez #define _DT_BINDINGS_MFD_STM32F7_RCC_H 8156fdf11SGabriel Fernandez 9156fdf11SGabriel Fernandez /* AHB1 */ 10156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOA 0 11156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOB 1 12156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOC 2 13156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOD 3 14156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOE 4 15156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOF 5 16156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOG 6 17156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOH 7 18156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOI 8 19156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOJ 9 20156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_GPIOK 10 21156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_CRC 12 22156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_BKPSRAM 18 23156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DTCMRAM 20 24156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA1 21 25156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA2 22 26156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_DMA2D 23 27156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMAC 25 28156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMACTX 26 29156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_ETHMACRX 27 30156fdf11SGabriel Fernandez #define STM32FF_RCC_AHB1_ETHMACPTP 28 31156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_OTGHS 29 32156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB1_OTGHSULPI 30 33156fdf11SGabriel Fernandez 34156fdf11SGabriel Fernandez #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) 35156fdf11SGabriel Fernandez #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) 36156fdf11SGabriel Fernandez 37156fdf11SGabriel Fernandez 38156fdf11SGabriel Fernandez /* AHB2 */ 39156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_DCMI 0 40156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_CRYP 4 41156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_HASH 5 42156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_RNG 6 43156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB2_OTGFS 7 44156fdf11SGabriel Fernandez 45156fdf11SGabriel Fernandez #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) 46156fdf11SGabriel Fernandez #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) 47156fdf11SGabriel Fernandez 48156fdf11SGabriel Fernandez /* AHB3 */ 49156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB3_FMC 0 50156fdf11SGabriel Fernandez #define STM32F7_RCC_AHB3_QSPI 1 51156fdf11SGabriel Fernandez 52156fdf11SGabriel Fernandez #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) 53156fdf11SGabriel Fernandez #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) 54156fdf11SGabriel Fernandez 55156fdf11SGabriel Fernandez /* APB1 */ 56156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM2 0 57156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM3 1 58156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM4 2 59156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM5 3 60156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM6 4 61156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM7 5 62156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM12 6 63156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM13 7 64156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_TIM14 8 65156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_LPTIM1 9 66156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_WWDG 11 67*8f3ef556SDario Binacchi #define STM32F7_RCC_APB1_CAN3 13 68156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPI2 14 69156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPI3 15 70156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_SPDIFRX 16 71156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART2 17 72156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART3 18 73156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART4 19 74156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART5 20 75156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C1 21 76156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C2 22 77156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C3 23 78156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_I2C4 24 79156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CAN1 25 80156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CAN2 26 81156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_CEC 27 82156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_PWR 28 83156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_DAC 29 84156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART7 30 85156fdf11SGabriel Fernandez #define STM32F7_RCC_APB1_UART8 31 86156fdf11SGabriel Fernandez 87156fdf11SGabriel Fernandez #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) 88156fdf11SGabriel Fernandez #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) 89156fdf11SGabriel Fernandez 90156fdf11SGabriel Fernandez /* APB2 */ 91156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM1 0 92156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM8 1 93156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_USART1 4 94156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_USART6 5 95f932423cSPatrice Chotard #define STM32F7_RCC_APB2_SDMMC2 7 96156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC1 8 97156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC2 9 98156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_ADC3 10 99156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SDMMC1 11 100156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI1 12 101156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI4 13 102156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SYSCFG 14 103156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM9 16 104156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM10 17 105156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_TIM11 18 106156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI5 20 107156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SPI6 21 108156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SAI1 22 109156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_SAI2 23 110156fdf11SGabriel Fernandez #define STM32F7_RCC_APB2_LTDC 26 111156fdf11SGabriel Fernandez 112156fdf11SGabriel Fernandez #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) 113156fdf11SGabriel Fernandez #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) 114156fdf11SGabriel Fernandez 115156fdf11SGabriel Fernandez #endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ 116