1ca9f71f0SMaxime Coquelin /* 2ca9f71f0SMaxime Coquelin * This header provides constants for the STM32F4 RCC IP 3ca9f71f0SMaxime Coquelin */ 4ca9f71f0SMaxime Coquelin 5ca9f71f0SMaxime Coquelin #ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H 6ca9f71f0SMaxime Coquelin #define _DT_BINDINGS_MFD_STM32F4_RCC_H 7ca9f71f0SMaxime Coquelin 8ca9f71f0SMaxime Coquelin /* AHB1 */ 9ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOA 0 10ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOB 1 11ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOC 2 12ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOD 3 13ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOE 4 14ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOF 5 15ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOG 6 16ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOH 7 17ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOI 8 18ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOJ 9 19ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOK 10 20ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_CRC 12 21ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA1 21 22ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA2 22 23ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA2D 23 24ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_ETHMAC 25 25ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_OTGHS 29 26ca9f71f0SMaxime Coquelin 27ca9f71f0SMaxime Coquelin #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) 28ca9f71f0SMaxime Coquelin #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit + (0x30 * 8)) 29ca9f71f0SMaxime Coquelin 30ca9f71f0SMaxime Coquelin 31ca9f71f0SMaxime Coquelin /* AHB2 */ 32ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_DCMI 0 33ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_CRYP 4 34ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_HASH 5 35ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_RNG 6 36ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_OTGFS 7 37ca9f71f0SMaxime Coquelin 38ca9f71f0SMaxime Coquelin #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) 39ca9f71f0SMaxime Coquelin #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + (0x34 * 8)) 40ca9f71f0SMaxime Coquelin 41ca9f71f0SMaxime Coquelin /* AHB3 */ 42ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB3_FMC 0 43ca9f71f0SMaxime Coquelin 44ca9f71f0SMaxime Coquelin #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) 45ca9f71f0SMaxime Coquelin #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + (0x38 * 8)) 46ca9f71f0SMaxime Coquelin 47ca9f71f0SMaxime Coquelin /* APB1 */ 48ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM2 0 49ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM3 1 50ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM4 2 51ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM5 3 52ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM6 4 53ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM7 5 54ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM12 6 55ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM13 7 56ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM14 8 57ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_WWDG 11 58ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_SPI2 14 59ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_SPI3 15 60ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART2 17 61ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART3 18 62ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART4 19 63ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART5 20 64ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C1 21 65ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C2 22 66ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C3 23 67ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_CAN1 25 68ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_CAN2 26 69ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_PWR 28 70ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_DAC 29 71ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART7 30 72ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART8 31 73ca9f71f0SMaxime Coquelin 74ca9f71f0SMaxime Coquelin #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) 75ca9f71f0SMaxime Coquelin #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + (0x40 * 8)) 76ca9f71f0SMaxime Coquelin 77ca9f71f0SMaxime Coquelin /* APB2 */ 78ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM1 0 79ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM8 1 80ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_USART1 4 81ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_USART6 5 82ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_ADC 8 83ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SDIO 11 84ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI1 12 85ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI4 13 86ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SYSCFG 14 87ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM9 16 88ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM10 17 89ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM11 18 90ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI5 20 91ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI6 21 92ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SAI1 22 93ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_LTDC 26 94ca9f71f0SMaxime Coquelin 95ca9f71f0SMaxime Coquelin #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) 96ca9f71f0SMaxime Coquelin #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + (0x44 * 8)) 97ca9f71f0SMaxime Coquelin 98ca9f71f0SMaxime Coquelin #endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ 99