1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ca9f71f0SMaxime Coquelin /* 3ca9f71f0SMaxime Coquelin * This header provides constants for the STM32F4 RCC IP 4ca9f71f0SMaxime Coquelin */ 5ca9f71f0SMaxime Coquelin 6ca9f71f0SMaxime Coquelin #ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H 7ca9f71f0SMaxime Coquelin #define _DT_BINDINGS_MFD_STM32F4_RCC_H 8ca9f71f0SMaxime Coquelin 9ca9f71f0SMaxime Coquelin /* AHB1 */ 10ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOA 0 11ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOB 1 12ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOC 2 13ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOD 3 14ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOE 4 15ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOF 5 16ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOG 6 17ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOH 7 18ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOI 8 19ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOJ 9 20ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_GPIOK 10 21ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_CRC 12 222cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_BKPSRAM 18 232cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_CCMDATARAM 20 24ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA1 21 25ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA2 22 26ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_DMA2D 23 27ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_ETHMAC 25 282cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_ETHMACTX 26 292cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_ETHMACRX 27 302cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_ETHMACPTP 28 31ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB1_OTGHS 29 322cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB1_OTGHSULPI 30 33ca9f71f0SMaxime Coquelin 34ca9f71f0SMaxime Coquelin #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) 35982b1592SGabriel Fernandez #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) 36ca9f71f0SMaxime Coquelin 37ca9f71f0SMaxime Coquelin 38ca9f71f0SMaxime Coquelin /* AHB2 */ 39ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_DCMI 0 40ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_CRYP 4 41ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_HASH 5 42ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_RNG 6 43ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB2_OTGFS 7 44ca9f71f0SMaxime Coquelin 45ca9f71f0SMaxime Coquelin #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) 46982b1592SGabriel Fernandez #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) 47ca9f71f0SMaxime Coquelin 48ca9f71f0SMaxime Coquelin /* AHB3 */ 49ca9f71f0SMaxime Coquelin #define STM32F4_RCC_AHB3_FMC 0 502cfb397bSGabriel Fernandez #define STM32F4_RCC_AHB3_QSPI 1 51ca9f71f0SMaxime Coquelin 52ca9f71f0SMaxime Coquelin #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) 53982b1592SGabriel Fernandez #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) 54ca9f71f0SMaxime Coquelin 55ca9f71f0SMaxime Coquelin /* APB1 */ 56ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM2 0 57ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM3 1 58ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM4 2 59ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM5 3 60ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM6 4 61ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM7 5 62ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM12 6 63ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM13 7 64ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_TIM14 8 65ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_WWDG 11 66ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_SPI2 14 67ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_SPI3 15 68ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART2 17 69ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART3 18 70ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART4 19 71ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART5 20 72ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C1 21 73ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C2 22 74ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_I2C3 23 75ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_CAN1 25 76ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_CAN2 26 77ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_PWR 28 78ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_DAC 29 79ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART7 30 80ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB1_UART8 31 81ca9f71f0SMaxime Coquelin 82ca9f71f0SMaxime Coquelin #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) 83982b1592SGabriel Fernandez #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) 84ca9f71f0SMaxime Coquelin 85ca9f71f0SMaxime Coquelin /* APB2 */ 86ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM1 0 87ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM8 1 88ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_USART1 4 89ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_USART6 5 902cfb397bSGabriel Fernandez #define STM32F4_RCC_APB2_ADC1 8 912cfb397bSGabriel Fernandez #define STM32F4_RCC_APB2_ADC2 9 922cfb397bSGabriel Fernandez #define STM32F4_RCC_APB2_ADC3 10 93ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SDIO 11 94ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI1 12 95ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI4 13 96ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SYSCFG 14 97ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM9 16 98ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM10 17 99ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_TIM11 18 100ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI5 20 101ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SPI6 21 102ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_SAI1 22 103ca9f71f0SMaxime Coquelin #define STM32F4_RCC_APB2_LTDC 26 1042cfb397bSGabriel Fernandez #define STM32F4_RCC_APB2_DSI 27 105ca9f71f0SMaxime Coquelin 106ca9f71f0SMaxime Coquelin #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) 107982b1592SGabriel Fernandez #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) 108ca9f71f0SMaxime Coquelin 109ca9f71f0SMaxime Coquelin #endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ 110