1f35f6225SXing Zheng /* 2f35f6225SXing Zheng * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3f35f6225SXing Zheng * Author: Xing Zheng <zhengxing@rock-chips.com> 4f35f6225SXing Zheng * 5f35f6225SXing Zheng * This program is free software; you can redistribute it and/or modify 6f35f6225SXing Zheng * it under the terms of the GNU General Public License as published by 7f35f6225SXing Zheng * the Free Software Foundation; either version 2 of the License, or 8f35f6225SXing Zheng * (at your option) any later version. 9f35f6225SXing Zheng * 10f35f6225SXing Zheng * This program is distributed in the hope that it will be useful, 11f35f6225SXing Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 12f35f6225SXing Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13f35f6225SXing Zheng * GNU General Public License for more details. 14f35f6225SXing Zheng */ 15f35f6225SXing Zheng 16f35f6225SXing Zheng #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 17f35f6225SXing Zheng #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 18f35f6225SXing Zheng 19f35f6225SXing Zheng /* core clocks */ 20f35f6225SXing Zheng #define PLL_APLLL 1 21f35f6225SXing Zheng #define PLL_APLLB 2 22f35f6225SXing Zheng #define PLL_DPLL 3 23f35f6225SXing Zheng #define PLL_CPLL 4 24f35f6225SXing Zheng #define PLL_GPLL 5 25f35f6225SXing Zheng #define PLL_NPLL 6 26f35f6225SXing Zheng #define PLL_VPLL 7 27f35f6225SXing Zheng #define ARMCLKL 8 28f35f6225SXing Zheng #define ARMCLKB 9 29f35f6225SXing Zheng 30f35f6225SXing Zheng /* sclk gates (special clocks) */ 31f35f6225SXing Zheng #define SCLK_I2C1 65 32f35f6225SXing Zheng #define SCLK_I2C2 66 33f35f6225SXing Zheng #define SCLK_I2C3 67 34f35f6225SXing Zheng #define SCLK_I2C5 68 35f35f6225SXing Zheng #define SCLK_I2C6 69 36f35f6225SXing Zheng #define SCLK_I2C7 70 37f35f6225SXing Zheng #define SCLK_SPI0 71 38f35f6225SXing Zheng #define SCLK_SPI1 72 39f35f6225SXing Zheng #define SCLK_SPI2 73 40f35f6225SXing Zheng #define SCLK_SPI4 74 41f35f6225SXing Zheng #define SCLK_SPI5 75 42f35f6225SXing Zheng #define SCLK_SDMMC 76 43f35f6225SXing Zheng #define SCLK_SDIO 77 44f35f6225SXing Zheng #define SCLK_EMMC 78 45f35f6225SXing Zheng #define SCLK_TSADC 79 46f35f6225SXing Zheng #define SCLK_SARADC 80 47f35f6225SXing Zheng #define SCLK_UART0 81 48f35f6225SXing Zheng #define SCLK_UART1 82 49f35f6225SXing Zheng #define SCLK_UART2 83 50f35f6225SXing Zheng #define SCLK_UART3 84 51f35f6225SXing Zheng #define SCLK_SPDIF_8CH 85 52f35f6225SXing Zheng #define SCLK_I2S0_8CH 86 53f35f6225SXing Zheng #define SCLK_I2S1_8CH 87 54f35f6225SXing Zheng #define SCLK_I2S2_8CH 88 55f35f6225SXing Zheng #define SCLK_I2S_8CH_OUT 89 56f35f6225SXing Zheng #define SCLK_TIMER00 90 57f35f6225SXing Zheng #define SCLK_TIMER01 91 58f35f6225SXing Zheng #define SCLK_TIMER02 92 59f35f6225SXing Zheng #define SCLK_TIMER03 93 60f35f6225SXing Zheng #define SCLK_TIMER04 94 61f35f6225SXing Zheng #define SCLK_TIMER05 95 62f35f6225SXing Zheng #define SCLK_TIMER06 96 63f35f6225SXing Zheng #define SCLK_TIMER07 97 64f35f6225SXing Zheng #define SCLK_TIMER08 98 65f35f6225SXing Zheng #define SCLK_TIMER09 99 66f35f6225SXing Zheng #define SCLK_TIMER10 100 67f35f6225SXing Zheng #define SCLK_TIMER11 101 68f35f6225SXing Zheng #define SCLK_MACREF 102 69f35f6225SXing Zheng #define SCLK_MAC_RX 103 70f35f6225SXing Zheng #define SCLK_MAC_TX 104 71f35f6225SXing Zheng #define SCLK_MAC 105 72f35f6225SXing Zheng #define SCLK_MACREF_OUT 106 73f35f6225SXing Zheng #define SCLK_VOP0_PWM 107 74f35f6225SXing Zheng #define SCLK_VOP1_PWM 108 75003e6eb7SXing Zheng #define SCLK_RGA_CORE 109 76f35f6225SXing Zheng #define SCLK_ISP0 110 77f35f6225SXing Zheng #define SCLK_ISP1 111 78f35f6225SXing Zheng #define SCLK_HDMI_CEC 112 79f35f6225SXing Zheng #define SCLK_HDMI_SFR 113 80f35f6225SXing Zheng #define SCLK_DP_CORE 114 81f35f6225SXing Zheng #define SCLK_PVTM_CORE_L 115 82f35f6225SXing Zheng #define SCLK_PVTM_CORE_B 116 83f35f6225SXing Zheng #define SCLK_PVTM_GPU 117 84f35f6225SXing Zheng #define SCLK_PVTM_DDR 118 85f35f6225SXing Zheng #define SCLK_MIPIDPHY_REF 119 86f35f6225SXing Zheng #define SCLK_MIPIDPHY_CFG 120 87f35f6225SXing Zheng #define SCLK_HSICPHY 121 88f35f6225SXing Zheng #define SCLK_USBPHY480M 122 89f35f6225SXing Zheng #define SCLK_USB2PHY0_REF 123 90f35f6225SXing Zheng #define SCLK_USB2PHY1_REF 124 91f35f6225SXing Zheng #define SCLK_UPHY0_TCPDPHY_REF 125 92f35f6225SXing Zheng #define SCLK_UPHY0_TCPDCORE 126 93f35f6225SXing Zheng #define SCLK_UPHY1_TCPDPHY_REF 127 94f35f6225SXing Zheng #define SCLK_UPHY1_TCPDCORE 128 95f35f6225SXing Zheng #define SCLK_USB3OTG0_REF 129 96f35f6225SXing Zheng #define SCLK_USB3OTG1_REF 130 97f35f6225SXing Zheng #define SCLK_USB3OTG0_SUSPEND 131 98f35f6225SXing Zheng #define SCLK_USB3OTG1_SUSPEND 132 99f35f6225SXing Zheng #define SCLK_CRYPTO0 133 100f35f6225SXing Zheng #define SCLK_CRYPTO1 134 101f35f6225SXing Zheng #define SCLK_CCI_TRACE 135 102f35f6225SXing Zheng #define SCLK_CS 136 103f35f6225SXing Zheng #define SCLK_CIF_OUT 137 104f35f6225SXing Zheng #define SCLK_PCIEPHY_REF 138 105f35f6225SXing Zheng #define SCLK_PCIE_CORE 139 106f35f6225SXing Zheng #define SCLK_M0_PERILP 140 107f35f6225SXing Zheng #define SCLK_M0_PERILP_DEC 141 108f35f6225SXing Zheng #define SCLK_CM0S 142 109f35f6225SXing Zheng #define SCLK_DBG_NOC 143 110f35f6225SXing Zheng #define SCLK_DBG_PD_CORE_B 144 111f35f6225SXing Zheng #define SCLK_DBG_PD_CORE_L 145 112f35f6225SXing Zheng #define SCLK_DFIMON0_TIMER 146 113f35f6225SXing Zheng #define SCLK_DFIMON1_TIMER 147 114f35f6225SXing Zheng #define SCLK_INTMEM0 148 115f35f6225SXing Zheng #define SCLK_INTMEM1 149 116f35f6225SXing Zheng #define SCLK_INTMEM2 150 117f35f6225SXing Zheng #define SCLK_INTMEM3 151 118f35f6225SXing Zheng #define SCLK_INTMEM4 152 119f35f6225SXing Zheng #define SCLK_INTMEM5 153 120f35f6225SXing Zheng #define SCLK_SDMMC_DRV 154 121f35f6225SXing Zheng #define SCLK_SDMMC_SAMPLE 155 122f35f6225SXing Zheng #define SCLK_SDIO_DRV 156 123f35f6225SXing Zheng #define SCLK_SDIO_SAMPLE 157 124f35f6225SXing Zheng #define SCLK_VDU_CORE 158 125f35f6225SXing Zheng #define SCLK_VDU_CA 159 126f35f6225SXing Zheng #define SCLK_PCIE_PM 160 127f35f6225SXing Zheng #define SCLK_SPDIF_REC_DPTX 161 128f35f6225SXing Zheng #define SCLK_DPHY_PLL 162 129f35f6225SXing Zheng #define SCLK_DPHY_TX0_CFG 163 130f35f6225SXing Zheng #define SCLK_DPHY_TX1RX1_CFG 164 131f35f6225SXing Zheng #define SCLK_DPHY_RX0_CFG 165 13255df4584SXing Zheng #define SCLK_RMII_SRC 166 13355df4584SXing Zheng #define SCLK_PCIEPHY_REF100M 167 1347fbdfcd6SLin Huang #define SCLK_DDRC 168 135f35f6225SXing Zheng 136f35f6225SXing Zheng #define DCLK_VOP0 180 137f35f6225SXing Zheng #define DCLK_VOP1 181 138f35f6225SXing Zheng #define DCLK_VOP0_DIV 182 139f35f6225SXing Zheng #define DCLK_VOP1_DIV 183 140f35f6225SXing Zheng #define DCLK_M0_PERILP 184 141e33075dbSYakir Yang #define DCLK_VOP0_FRAC 185 142e33075dbSYakir Yang #define DCLK_VOP1_FRAC 186 143f35f6225SXing Zheng 144f35f6225SXing Zheng #define FCLK_CM0S 190 145f35f6225SXing Zheng 146f35f6225SXing Zheng /* aclk gates */ 147f35f6225SXing Zheng #define ACLK_PERIHP 192 148f35f6225SXing Zheng #define ACLK_PERIHP_NOC 193 149f35f6225SXing Zheng #define ACLK_PERILP0 194 150f35f6225SXing Zheng #define ACLK_PERILP0_NOC 195 151f35f6225SXing Zheng #define ACLK_PERF_PCIE 196 152f35f6225SXing Zheng #define ACLK_PCIE 197 153f35f6225SXing Zheng #define ACLK_INTMEM 198 154f35f6225SXing Zheng #define ACLK_TZMA 199 155f35f6225SXing Zheng #define ACLK_DCF 200 156f35f6225SXing Zheng #define ACLK_CCI 201 157f35f6225SXing Zheng #define ACLK_CCI_NOC0 202 158f35f6225SXing Zheng #define ACLK_CCI_NOC1 203 159f35f6225SXing Zheng #define ACLK_CCI_GRF 204 160f35f6225SXing Zheng #define ACLK_CENTER 205 161f35f6225SXing Zheng #define ACLK_CENTER_MAIN_NOC 206 162f35f6225SXing Zheng #define ACLK_CENTER_PERI_NOC 207 163f35f6225SXing Zheng #define ACLK_GPU 208 164f35f6225SXing Zheng #define ACLK_PERF_GPU 209 165f35f6225SXing Zheng #define ACLK_GPU_GRF 210 166f35f6225SXing Zheng #define ACLK_DMAC0_PERILP 211 167f35f6225SXing Zheng #define ACLK_DMAC1_PERILP 212 168f35f6225SXing Zheng #define ACLK_GMAC 213 169f35f6225SXing Zheng #define ACLK_GMAC_NOC 214 170f35f6225SXing Zheng #define ACLK_PERF_GMAC 215 171f35f6225SXing Zheng #define ACLK_VOP0_NOC 216 172f35f6225SXing Zheng #define ACLK_VOP0 217 173f35f6225SXing Zheng #define ACLK_VOP1_NOC 218 174f35f6225SXing Zheng #define ACLK_VOP1 219 175f35f6225SXing Zheng #define ACLK_RGA 220 176f35f6225SXing Zheng #define ACLK_RGA_NOC 221 177f35f6225SXing Zheng #define ACLK_HDCP 222 178f35f6225SXing Zheng #define ACLK_HDCP_NOC 223 179f35f6225SXing Zheng #define ACLK_HDCP22 224 180f35f6225SXing Zheng #define ACLK_IEP 225 181f35f6225SXing Zheng #define ACLK_IEP_NOC 226 182f35f6225SXing Zheng #define ACLK_VIO 227 183f35f6225SXing Zheng #define ACLK_VIO_NOC 228 184f35f6225SXing Zheng #define ACLK_ISP0 229 185f35f6225SXing Zheng #define ACLK_ISP1 230 186f35f6225SXing Zheng #define ACLK_ISP0_NOC 231 187f35f6225SXing Zheng #define ACLK_ISP1_NOC 232 188f35f6225SXing Zheng #define ACLK_ISP0_WRAPPER 233 189f35f6225SXing Zheng #define ACLK_ISP1_WRAPPER 234 190f35f6225SXing Zheng #define ACLK_VCODEC 235 191f35f6225SXing Zheng #define ACLK_VCODEC_NOC 236 192f35f6225SXing Zheng #define ACLK_VDU 237 193f35f6225SXing Zheng #define ACLK_VDU_NOC 238 194f35f6225SXing Zheng #define ACLK_PERI 239 195f35f6225SXing Zheng #define ACLK_EMMC 240 196f35f6225SXing Zheng #define ACLK_EMMC_CORE 241 197f35f6225SXing Zheng #define ACLK_EMMC_NOC 242 198f35f6225SXing Zheng #define ACLK_EMMC_GRF 243 199f35f6225SXing Zheng #define ACLK_USB3 244 200f35f6225SXing Zheng #define ACLK_USB3_NOC 245 201f35f6225SXing Zheng #define ACLK_USB3OTG0 246 202f35f6225SXing Zheng #define ACLK_USB3OTG1 247 203f35f6225SXing Zheng #define ACLK_USB3_RKSOC_AXI_PERF 248 204f35f6225SXing Zheng #define ACLK_USB3_GRF 249 205f35f6225SXing Zheng #define ACLK_GIC 250 206f35f6225SXing Zheng #define ACLK_GIC_NOC 251 207f35f6225SXing Zheng #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 208f35f6225SXing Zheng #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 209f35f6225SXing Zheng #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 210f35f6225SXing Zheng #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 211f35f6225SXing Zheng #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 212f35f6225SXing Zheng #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 213f35f6225SXing Zheng #define ACLK_ADB400M_PD_CORE_L 258 214f35f6225SXing Zheng #define ACLK_ADB400M_PD_CORE_B 259 215f35f6225SXing Zheng #define ACLK_PERF_CORE_L 260 216f35f6225SXing Zheng #define ACLK_PERF_CORE_B 261 217f35f6225SXing Zheng #define ACLK_GIC_PRE 262 218f35f6225SXing Zheng #define ACLK_VOP0_PRE 263 219f35f6225SXing Zheng #define ACLK_VOP1_PRE 264 220f35f6225SXing Zheng 221f35f6225SXing Zheng /* pclk gates */ 222f35f6225SXing Zheng #define PCLK_PERIHP 320 223f35f6225SXing Zheng #define PCLK_PERIHP_NOC 321 224f35f6225SXing Zheng #define PCLK_PERILP0 322 225f35f6225SXing Zheng #define PCLK_PERILP1 323 226f35f6225SXing Zheng #define PCLK_PERILP1_NOC 324 227f35f6225SXing Zheng #define PCLK_PERILP_SGRF 325 228f35f6225SXing Zheng #define PCLK_PERIHP_GRF 326 229f35f6225SXing Zheng #define PCLK_PCIE 327 230f35f6225SXing Zheng #define PCLK_SGRF 328 231f35f6225SXing Zheng #define PCLK_INTR_ARB 329 232f35f6225SXing Zheng #define PCLK_CENTER_MAIN_NOC 330 233f35f6225SXing Zheng #define PCLK_CIC 331 234f35f6225SXing Zheng #define PCLK_COREDBG_B 332 235f35f6225SXing Zheng #define PCLK_COREDBG_L 333 236f35f6225SXing Zheng #define PCLK_DBG_CXCS_PD_CORE_B 334 237f35f6225SXing Zheng #define PCLK_DCF 335 238f35f6225SXing Zheng #define PCLK_GPIO2 336 239f35f6225SXing Zheng #define PCLK_GPIO3 337 240f35f6225SXing Zheng #define PCLK_GPIO4 338 241f35f6225SXing Zheng #define PCLK_GRF 339 242f35f6225SXing Zheng #define PCLK_HSICPHY 340 243f35f6225SXing Zheng #define PCLK_I2C1 341 244f35f6225SXing Zheng #define PCLK_I2C2 342 245f35f6225SXing Zheng #define PCLK_I2C3 343 246f35f6225SXing Zheng #define PCLK_I2C5 344 247f35f6225SXing Zheng #define PCLK_I2C6 345 248f35f6225SXing Zheng #define PCLK_I2C7 346 249f35f6225SXing Zheng #define PCLK_SPI0 347 250f35f6225SXing Zheng #define PCLK_SPI1 348 251f35f6225SXing Zheng #define PCLK_SPI2 349 252f35f6225SXing Zheng #define PCLK_SPI4 350 253f35f6225SXing Zheng #define PCLK_SPI5 351 254f35f6225SXing Zheng #define PCLK_UART0 352 255f35f6225SXing Zheng #define PCLK_UART1 353 256f35f6225SXing Zheng #define PCLK_UART2 354 257f35f6225SXing Zheng #define PCLK_UART3 355 258f35f6225SXing Zheng #define PCLK_TSADC 356 259f35f6225SXing Zheng #define PCLK_SARADC 357 260f35f6225SXing Zheng #define PCLK_GMAC 358 261f35f6225SXing Zheng #define PCLK_GMAC_NOC 359 262f35f6225SXing Zheng #define PCLK_TIMER0 360 263f35f6225SXing Zheng #define PCLK_TIMER1 361 264f35f6225SXing Zheng #define PCLK_EDP 362 265f35f6225SXing Zheng #define PCLK_EDP_NOC 363 266f35f6225SXing Zheng #define PCLK_EDP_CTRL 364 267f35f6225SXing Zheng #define PCLK_VIO 365 268f35f6225SXing Zheng #define PCLK_VIO_NOC 366 269f35f6225SXing Zheng #define PCLK_VIO_GRF 367 270f35f6225SXing Zheng #define PCLK_MIPI_DSI0 368 271f35f6225SXing Zheng #define PCLK_MIPI_DSI1 369 272f35f6225SXing Zheng #define PCLK_HDCP 370 273f35f6225SXing Zheng #define PCLK_HDCP_NOC 371 274f35f6225SXing Zheng #define PCLK_HDMI_CTRL 372 275f35f6225SXing Zheng #define PCLK_DP_CTRL 373 276f35f6225SXing Zheng #define PCLK_HDCP22 374 277f35f6225SXing Zheng #define PCLK_GASKET 375 278f35f6225SXing Zheng #define PCLK_DDR 376 279f35f6225SXing Zheng #define PCLK_DDR_MON 377 280f35f6225SXing Zheng #define PCLK_DDR_SGRF 378 281f35f6225SXing Zheng #define PCLK_ISP1_WRAPPER 379 282f35f6225SXing Zheng #define PCLK_WDT 380 283f35f6225SXing Zheng #define PCLK_EFUSE1024NS 381 284f35f6225SXing Zheng #define PCLK_EFUSE1024S 382 285f35f6225SXing Zheng #define PCLK_PMU_INTR_ARB 383 286f35f6225SXing Zheng #define PCLK_MAILBOX0 384 287f35f6225SXing Zheng #define PCLK_USBPHY_MUX_G 385 288f35f6225SXing Zheng #define PCLK_UPHY0_TCPHY_G 386 289f35f6225SXing Zheng #define PCLK_UPHY0_TCPD_G 387 290f35f6225SXing Zheng #define PCLK_UPHY1_TCPHY_G 388 291f35f6225SXing Zheng #define PCLK_UPHY1_TCPD_G 389 292f35f6225SXing Zheng #define PCLK_ALIVE 390 293f35f6225SXing Zheng 294f35f6225SXing Zheng /* hclk gates */ 295f35f6225SXing Zheng #define HCLK_PERIHP 448 296f35f6225SXing Zheng #define HCLK_PERILP0 449 297f35f6225SXing Zheng #define HCLK_PERILP1 450 298f35f6225SXing Zheng #define HCLK_PERILP0_NOC 451 299f35f6225SXing Zheng #define HCLK_PERILP1_NOC 452 300f35f6225SXing Zheng #define HCLK_M0_PERILP 453 301f35f6225SXing Zheng #define HCLK_M0_PERILP_NOC 454 302f35f6225SXing Zheng #define HCLK_AHB1TOM 455 303f35f6225SXing Zheng #define HCLK_HOST0 456 304f35f6225SXing Zheng #define HCLK_HOST0_ARB 457 305f35f6225SXing Zheng #define HCLK_HOST1 458 306f35f6225SXing Zheng #define HCLK_HOST1_ARB 459 307f35f6225SXing Zheng #define HCLK_HSIC 460 308f35f6225SXing Zheng #define HCLK_SD 461 309f35f6225SXing Zheng #define HCLK_SDMMC 462 310f35f6225SXing Zheng #define HCLK_SDMMC_NOC 463 311f35f6225SXing Zheng #define HCLK_M_CRYPTO0 464 312f35f6225SXing Zheng #define HCLK_M_CRYPTO1 465 313f35f6225SXing Zheng #define HCLK_S_CRYPTO0 466 314f35f6225SXing Zheng #define HCLK_S_CRYPTO1 467 315f35f6225SXing Zheng #define HCLK_I2S0_8CH 468 316f35f6225SXing Zheng #define HCLK_I2S1_8CH 469 317f35f6225SXing Zheng #define HCLK_I2S2_8CH 470 318f35f6225SXing Zheng #define HCLK_SPDIF 471 319f35f6225SXing Zheng #define HCLK_VOP0_NOC 472 320f35f6225SXing Zheng #define HCLK_VOP0 473 321f35f6225SXing Zheng #define HCLK_VOP1_NOC 474 322f35f6225SXing Zheng #define HCLK_VOP1 475 323f35f6225SXing Zheng #define HCLK_ROM 476 324f35f6225SXing Zheng #define HCLK_IEP 477 325f35f6225SXing Zheng #define HCLK_IEP_NOC 478 326f35f6225SXing Zheng #define HCLK_ISP0 479 327f35f6225SXing Zheng #define HCLK_ISP1 480 328f35f6225SXing Zheng #define HCLK_ISP0_NOC 481 329f35f6225SXing Zheng #define HCLK_ISP1_NOC 482 330f35f6225SXing Zheng #define HCLK_ISP0_WRAPPER 483 331f35f6225SXing Zheng #define HCLK_ISP1_WRAPPER 484 332f35f6225SXing Zheng #define HCLK_RGA 485 333f35f6225SXing Zheng #define HCLK_RGA_NOC 486 334f35f6225SXing Zheng #define HCLK_HDCP 487 335f35f6225SXing Zheng #define HCLK_HDCP_NOC 488 336f35f6225SXing Zheng #define HCLK_HDCP22 489 337f35f6225SXing Zheng #define HCLK_VCODEC 490 338f35f6225SXing Zheng #define HCLK_VCODEC_NOC 491 339f35f6225SXing Zheng #define HCLK_VDU 492 340f35f6225SXing Zheng #define HCLK_VDU_NOC 493 341f35f6225SXing Zheng #define HCLK_SDIO 494 342f35f6225SXing Zheng #define HCLK_SDIO_NOC 495 343f35f6225SXing Zheng #define HCLK_SDIOAUDIO_NOC 496 344f35f6225SXing Zheng 345f35f6225SXing Zheng #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 346f35f6225SXing Zheng 347f35f6225SXing Zheng /* pmu-clocks indices */ 348f35f6225SXing Zheng 349f35f6225SXing Zheng #define PLL_PPLL 1 350f35f6225SXing Zheng 351f35f6225SXing Zheng #define SCLK_32K_SUSPEND_PMU 2 352f35f6225SXing Zheng #define SCLK_SPI3_PMU 3 353f35f6225SXing Zheng #define SCLK_TIMER12_PMU 4 354f35f6225SXing Zheng #define SCLK_TIMER13_PMU 5 355f35f6225SXing Zheng #define SCLK_UART4_PMU 6 356f35f6225SXing Zheng #define SCLK_PVTM_PMU 7 357f35f6225SXing Zheng #define SCLK_WIFI_PMU 8 358f35f6225SXing Zheng #define SCLK_I2C0_PMU 9 359f35f6225SXing Zheng #define SCLK_I2C4_PMU 10 360f35f6225SXing Zheng #define SCLK_I2C8_PMU 11 361f35f6225SXing Zheng 362f35f6225SXing Zheng #define PCLK_SRC_PMU 19 363f35f6225SXing Zheng #define PCLK_PMU 20 364f35f6225SXing Zheng #define PCLK_PMUGRF_PMU 21 365f35f6225SXing Zheng #define PCLK_INTMEM1_PMU 22 366f35f6225SXing Zheng #define PCLK_GPIO0_PMU 23 367f35f6225SXing Zheng #define PCLK_GPIO1_PMU 24 368f35f6225SXing Zheng #define PCLK_SGRF_PMU 25 369f35f6225SXing Zheng #define PCLK_NOC_PMU 26 370f35f6225SXing Zheng #define PCLK_I2C0_PMU 27 371f35f6225SXing Zheng #define PCLK_I2C4_PMU 28 372f35f6225SXing Zheng #define PCLK_I2C8_PMU 29 373f35f6225SXing Zheng #define PCLK_RKPWM_PMU 30 374f35f6225SXing Zheng #define PCLK_SPI3_PMU 31 375f35f6225SXing Zheng #define PCLK_TIMER_PMU 32 376f35f6225SXing Zheng #define PCLK_MAILBOX_PMU 33 377f35f6225SXing Zheng #define PCLK_UART4_PMU 34 378f35f6225SXing Zheng #define PCLK_WDT_M0_PMU 35 379f35f6225SXing Zheng 380f35f6225SXing Zheng #define FCLK_CM0S_SRC_PMU 44 381f35f6225SXing Zheng #define FCLK_CM0S_PMU 45 382f35f6225SXing Zheng #define SCLK_CM0S_PMU 46 383f35f6225SXing Zheng #define HCLK_CM0S_PMU 47 384f35f6225SXing Zheng #define DCLK_CM0S_PMU 48 385f35f6225SXing Zheng #define PCLK_INTR_ARB_PMU 49 386f35f6225SXing Zheng #define HCLK_NOC_PMU 50 387f35f6225SXing Zheng 388f35f6225SXing Zheng #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 389f35f6225SXing Zheng 390f35f6225SXing Zheng /* soft-reset indices */ 391f35f6225SXing Zheng 392f35f6225SXing Zheng /* cru_softrst_con0 */ 393f35f6225SXing Zheng #define SRST_CORE_L0 0 394f35f6225SXing Zheng #define SRST_CORE_B0 1 395f35f6225SXing Zheng #define SRST_CORE_PO_L0 2 396f35f6225SXing Zheng #define SRST_CORE_PO_B0 3 397f35f6225SXing Zheng #define SRST_L2_L 4 398f35f6225SXing Zheng #define SRST_L2_B 5 399f35f6225SXing Zheng #define SRST_ADB_L 6 400f35f6225SXing Zheng #define SRST_ADB_B 7 401f35f6225SXing Zheng #define SRST_A_CCI 8 402f35f6225SXing Zheng #define SRST_A_CCIM0_NOC 9 403f35f6225SXing Zheng #define SRST_A_CCIM1_NOC 10 404f35f6225SXing Zheng #define SRST_DBG_NOC 11 405f35f6225SXing Zheng 406f35f6225SXing Zheng /* cru_softrst_con1 */ 407f35f6225SXing Zheng #define SRST_CORE_L0_T 16 408f35f6225SXing Zheng #define SRST_CORE_L1 17 409f35f6225SXing Zheng #define SRST_CORE_L2 18 410f35f6225SXing Zheng #define SRST_CORE_L3 19 411f35f6225SXing Zheng #define SRST_CORE_PO_L0_T 20 412f35f6225SXing Zheng #define SRST_CORE_PO_L1 21 413f35f6225SXing Zheng #define SRST_CORE_PO_L2 22 414f35f6225SXing Zheng #define SRST_CORE_PO_L3 23 415f35f6225SXing Zheng #define SRST_A_ADB400_GIC2COREL 24 416f35f6225SXing Zheng #define SRST_A_ADB400_COREL2GIC 25 417f35f6225SXing Zheng #define SRST_P_DBG_L 26 418f35f6225SXing Zheng #define SRST_L2_L_T 28 419f35f6225SXing Zheng #define SRST_ADB_L_T 29 420f35f6225SXing Zheng #define SRST_A_RKPERF_L 30 421f35f6225SXing Zheng #define SRST_PVTM_CORE_L 31 422f35f6225SXing Zheng 423f35f6225SXing Zheng /* cru_softrst_con2 */ 424f35f6225SXing Zheng #define SRST_CORE_B0_T 32 425f35f6225SXing Zheng #define SRST_CORE_B1 33 426f35f6225SXing Zheng #define SRST_CORE_PO_B0_T 36 427f35f6225SXing Zheng #define SRST_CORE_PO_B1 37 428f35f6225SXing Zheng #define SRST_A_ADB400_GIC2COREB 40 429f35f6225SXing Zheng #define SRST_A_ADB400_COREB2GIC 41 430f35f6225SXing Zheng #define SRST_P_DBG_B 42 431f35f6225SXing Zheng #define SRST_L2_B_T 43 432f35f6225SXing Zheng #define SRST_ADB_B_T 45 433f35f6225SXing Zheng #define SRST_A_RKPERF_B 46 434f35f6225SXing Zheng #define SRST_PVTM_CORE_B 47 435f35f6225SXing Zheng 436f35f6225SXing Zheng /* cru_softrst_con3 */ 437f35f6225SXing Zheng #define SRST_A_CCI_T 50 438f35f6225SXing Zheng #define SRST_A_CCIM0_NOC_T 51 439f35f6225SXing Zheng #define SRST_A_CCIM1_NOC_T 52 440f35f6225SXing Zheng #define SRST_A_ADB400M_PD_CORE_B_T 53 441f35f6225SXing Zheng #define SRST_A_ADB400M_PD_CORE_L_T 54 442f35f6225SXing Zheng #define SRST_DBG_NOC_T 55 443f35f6225SXing Zheng #define SRST_DBG_CXCS 56 444f35f6225SXing Zheng #define SRST_CCI_TRACE 57 445f35f6225SXing Zheng #define SRST_P_CCI_GRF 58 446f35f6225SXing Zheng 447f35f6225SXing Zheng /* cru_softrst_con4 */ 448f35f6225SXing Zheng #define SRST_A_CENTER_MAIN_NOC 64 449f35f6225SXing Zheng #define SRST_A_CENTER_PERI_NOC 65 450f35f6225SXing Zheng #define SRST_P_CENTER_MAIN 66 451f35f6225SXing Zheng #define SRST_P_DDRMON 67 452f35f6225SXing Zheng #define SRST_P_CIC 68 453f35f6225SXing Zheng #define SRST_P_CENTER_SGRF 69 454f35f6225SXing Zheng #define SRST_DDR0_MSCH 70 455f35f6225SXing Zheng #define SRST_DDRCFG0_MSCH 71 456f35f6225SXing Zheng #define SRST_DDR0 72 457f35f6225SXing Zheng #define SRST_DDRPHY0 73 458f35f6225SXing Zheng #define SRST_DDR1_MSCH 74 459f35f6225SXing Zheng #define SRST_DDRCFG1_MSCH 75 460f35f6225SXing Zheng #define SRST_DDR1 76 461f35f6225SXing Zheng #define SRST_DDRPHY1 77 462f35f6225SXing Zheng #define SRST_DDR_CIC 78 463f35f6225SXing Zheng #define SRST_PVTM_DDR 79 464f35f6225SXing Zheng 465f35f6225SXing Zheng /* cru_softrst_con5 */ 466f35f6225SXing Zheng #define SRST_A_VCODEC_NOC 80 467f35f6225SXing Zheng #define SRST_A_VCODEC 81 468f35f6225SXing Zheng #define SRST_H_VCODEC_NOC 82 469f35f6225SXing Zheng #define SRST_H_VCODEC 83 470f35f6225SXing Zheng #define SRST_A_VDU_NOC 88 471f35f6225SXing Zheng #define SRST_A_VDU 89 472f35f6225SXing Zheng #define SRST_H_VDU_NOC 90 473f35f6225SXing Zheng #define SRST_H_VDU 91 474f35f6225SXing Zheng #define SRST_VDU_CORE 92 475f35f6225SXing Zheng #define SRST_VDU_CA 93 476f35f6225SXing Zheng 477f35f6225SXing Zheng /* cru_softrst_con6 */ 478f35f6225SXing Zheng #define SRST_A_IEP_NOC 96 479f35f6225SXing Zheng #define SRST_A_VOP_IEP 97 480f35f6225SXing Zheng #define SRST_A_IEP 98 481f35f6225SXing Zheng #define SRST_H_IEP_NOC 99 482f35f6225SXing Zheng #define SRST_H_IEP 100 483f35f6225SXing Zheng #define SRST_A_RGA_NOC 102 484f35f6225SXing Zheng #define SRST_A_RGA 103 485f35f6225SXing Zheng #define SRST_H_RGA_NOC 104 486f35f6225SXing Zheng #define SRST_H_RGA 105 487f35f6225SXing Zheng #define SRST_RGA_CORE 106 488f35f6225SXing Zheng #define SRST_EMMC_NOC 108 489f35f6225SXing Zheng #define SRST_EMMC 109 490f35f6225SXing Zheng #define SRST_EMMC_GRF 110 491f35f6225SXing Zheng 492f35f6225SXing Zheng /* cru_softrst_con7 */ 493f35f6225SXing Zheng #define SRST_A_PERIHP_NOC 112 494f35f6225SXing Zheng #define SRST_P_PERIHP_GRF 113 495f35f6225SXing Zheng #define SRST_H_PERIHP_NOC 114 496f35f6225SXing Zheng #define SRST_USBHOST0 115 497f35f6225SXing Zheng #define SRST_HOSTC0_AUX 116 498f35f6225SXing Zheng #define SRST_HOST0_ARB 117 499f35f6225SXing Zheng #define SRST_USBHOST1 118 500f35f6225SXing Zheng #define SRST_HOSTC1_AUX 119 501f35f6225SXing Zheng #define SRST_HOST1_ARB 120 502f35f6225SXing Zheng #define SRST_SDIO0 121 503f35f6225SXing Zheng #define SRST_SDMMC 122 504f35f6225SXing Zheng #define SRST_HSIC 123 505f35f6225SXing Zheng #define SRST_HSIC_AUX 124 506f35f6225SXing Zheng #define SRST_AHB1TOM 125 507f35f6225SXing Zheng #define SRST_P_PERIHP_NOC 126 508f35f6225SXing Zheng #define SRST_HSICPHY 127 509f35f6225SXing Zheng 510f35f6225SXing Zheng /* cru_softrst_con8 */ 511f35f6225SXing Zheng #define SRST_A_PCIE 128 512f35f6225SXing Zheng #define SRST_P_PCIE 129 513f35f6225SXing Zheng #define SRST_PCIE_CORE 130 514f35f6225SXing Zheng #define SRST_PCIE_MGMT 131 515f35f6225SXing Zheng #define SRST_PCIE_MGMT_STICKY 132 516f35f6225SXing Zheng #define SRST_PCIE_PIPE 133 517f35f6225SXing Zheng #define SRST_PCIE_PM 134 518f35f6225SXing Zheng #define SRST_PCIEPHY 135 519f35f6225SXing Zheng #define SRST_A_GMAC_NOC 136 520f35f6225SXing Zheng #define SRST_A_GMAC 137 521f35f6225SXing Zheng #define SRST_P_GMAC_NOC 138 522f35f6225SXing Zheng #define SRST_P_GMAC_GRF 140 523f35f6225SXing Zheng #define SRST_HSICPHY_POR 142 524f35f6225SXing Zheng #define SRST_HSICPHY_UTMI 143 525f35f6225SXing Zheng 526f35f6225SXing Zheng /* cru_softrst_con9 */ 527f35f6225SXing Zheng #define SRST_USB2PHY0_POR 144 528f35f6225SXing Zheng #define SRST_USB2PHY0_UTMI_PORT0 145 529f35f6225SXing Zheng #define SRST_USB2PHY0_UTMI_PORT1 146 530f35f6225SXing Zheng #define SRST_USB2PHY0_EHCIPHY 147 531f35f6225SXing Zheng #define SRST_UPHY0_PIPE_L00 148 532f35f6225SXing Zheng #define SRST_UPHY0 149 533f35f6225SXing Zheng #define SRST_UPHY0_TCPDPWRUP 150 534f35f6225SXing Zheng #define SRST_USB2PHY1_POR 152 535f35f6225SXing Zheng #define SRST_USB2PHY1_UTMI_PORT0 153 536f35f6225SXing Zheng #define SRST_USB2PHY1_UTMI_PORT1 154 537f35f6225SXing Zheng #define SRST_USB2PHY1_EHCIPHY 155 538f35f6225SXing Zheng #define SRST_UPHY1_PIPE_L00 156 539f35f6225SXing Zheng #define SRST_UPHY1 157 540f35f6225SXing Zheng #define SRST_UPHY1_TCPDPWRUP 158 541f35f6225SXing Zheng 542f35f6225SXing Zheng /* cru_softrst_con10 */ 543f35f6225SXing Zheng #define SRST_A_PERILP0_NOC 160 544f35f6225SXing Zheng #define SRST_A_DCF 161 545f35f6225SXing Zheng #define SRST_GIC500 162 546f35f6225SXing Zheng #define SRST_DMAC0_PERILP0 163 547f35f6225SXing Zheng #define SRST_DMAC1_PERILP0 164 548f35f6225SXing Zheng #define SRST_TZMA 165 549f35f6225SXing Zheng #define SRST_INTMEM 166 550f35f6225SXing Zheng #define SRST_ADB400_MST0 167 551f35f6225SXing Zheng #define SRST_ADB400_MST1 168 552f35f6225SXing Zheng #define SRST_ADB400_SLV0 169 553f35f6225SXing Zheng #define SRST_ADB400_SLV1 170 554f35f6225SXing Zheng #define SRST_H_PERILP0 171 555f35f6225SXing Zheng #define SRST_H_PERILP0_NOC 172 556f35f6225SXing Zheng #define SRST_ROM 173 557f35f6225SXing Zheng #define SRST_CRYPTO_S 174 558f35f6225SXing Zheng #define SRST_CRYPTO_M 175 559f35f6225SXing Zheng 560f35f6225SXing Zheng /* cru_softrst_con11 */ 561f35f6225SXing Zheng #define SRST_P_DCF 176 562f35f6225SXing Zheng #define SRST_CM0S_NOC 177 563f35f6225SXing Zheng #define SRST_CM0S 178 564f35f6225SXing Zheng #define SRST_CM0S_DBG 179 565f35f6225SXing Zheng #define SRST_CM0S_PO 180 566f35f6225SXing Zheng #define SRST_CRYPTO 181 567f35f6225SXing Zheng #define SRST_P_PERILP1_SGRF 182 568f35f6225SXing Zheng #define SRST_P_PERILP1_GRF 183 569f35f6225SXing Zheng #define SRST_CRYPTO1_S 184 570f35f6225SXing Zheng #define SRST_CRYPTO1_M 185 571f35f6225SXing Zheng #define SRST_CRYPTO1 186 572f35f6225SXing Zheng #define SRST_GIC_NOC 188 573f35f6225SXing Zheng #define SRST_SD_NOC 189 574f35f6225SXing Zheng #define SRST_SDIOAUDIO_BRG 190 575f35f6225SXing Zheng 576f35f6225SXing Zheng /* cru_softrst_con12 */ 577f35f6225SXing Zheng #define SRST_H_PERILP1 192 578f35f6225SXing Zheng #define SRST_H_PERILP1_NOC 193 579f35f6225SXing Zheng #define SRST_H_I2S0_8CH 194 580f35f6225SXing Zheng #define SRST_H_I2S1_8CH 195 581f35f6225SXing Zheng #define SRST_H_I2S2_8CH 196 582f35f6225SXing Zheng #define SRST_H_SPDIF_8CH 197 583f35f6225SXing Zheng #define SRST_P_PERILP1_NOC 198 584f35f6225SXing Zheng #define SRST_P_EFUSE_1024 199 585f35f6225SXing Zheng #define SRST_P_EFUSE_1024S 200 586f35f6225SXing Zheng #define SRST_P_I2C0 201 587f35f6225SXing Zheng #define SRST_P_I2C1 202 588f35f6225SXing Zheng #define SRST_P_I2C2 203 589f35f6225SXing Zheng #define SRST_P_I2C3 204 590f35f6225SXing Zheng #define SRST_P_I2C4 205 591f35f6225SXing Zheng #define SRST_P_I2C5 206 592f35f6225SXing Zheng #define SRST_P_MAILBOX0 207 593f35f6225SXing Zheng 594f35f6225SXing Zheng /* cru_softrst_con13 */ 595f35f6225SXing Zheng #define SRST_P_UART0 208 596f35f6225SXing Zheng #define SRST_P_UART1 209 597f35f6225SXing Zheng #define SRST_P_UART2 210 598f35f6225SXing Zheng #define SRST_P_UART3 211 599f35f6225SXing Zheng #define SRST_P_SARADC 212 600f35f6225SXing Zheng #define SRST_P_TSADC 213 601f35f6225SXing Zheng #define SRST_P_SPI0 214 602f35f6225SXing Zheng #define SRST_P_SPI1 215 603f35f6225SXing Zheng #define SRST_P_SPI2 216 604f35f6225SXing Zheng #define SRST_P_SPI3 217 605f35f6225SXing Zheng #define SRST_P_SPI4 218 606f35f6225SXing Zheng #define SRST_SPI0 219 607f35f6225SXing Zheng #define SRST_SPI1 220 608f35f6225SXing Zheng #define SRST_SPI2 221 609f35f6225SXing Zheng #define SRST_SPI3 222 610f35f6225SXing Zheng #define SRST_SPI4 223 611f35f6225SXing Zheng 612f35f6225SXing Zheng /* cru_softrst_con14 */ 613f35f6225SXing Zheng #define SRST_I2S0_8CH 224 614f35f6225SXing Zheng #define SRST_I2S1_8CH 225 615f35f6225SXing Zheng #define SRST_I2S2_8CH 226 616f35f6225SXing Zheng #define SRST_SPDIF_8CH 227 617f35f6225SXing Zheng #define SRST_UART0 228 618f35f6225SXing Zheng #define SRST_UART1 229 619f35f6225SXing Zheng #define SRST_UART2 230 620f35f6225SXing Zheng #define SRST_UART3 231 621f35f6225SXing Zheng #define SRST_TSADC 232 622f35f6225SXing Zheng #define SRST_I2C0 233 623f35f6225SXing Zheng #define SRST_I2C1 234 624f35f6225SXing Zheng #define SRST_I2C2 235 625f35f6225SXing Zheng #define SRST_I2C3 236 626f35f6225SXing Zheng #define SRST_I2C4 237 627f35f6225SXing Zheng #define SRST_I2C5 238 628f35f6225SXing Zheng #define SRST_SDIOAUDIO_NOC 239 629f35f6225SXing Zheng 630f35f6225SXing Zheng /* cru_softrst_con15 */ 631f35f6225SXing Zheng #define SRST_A_VIO_NOC 240 632f35f6225SXing Zheng #define SRST_A_HDCP_NOC 241 633f35f6225SXing Zheng #define SRST_A_HDCP 242 634f35f6225SXing Zheng #define SRST_H_HDCP_NOC 243 635f35f6225SXing Zheng #define SRST_H_HDCP 244 636f35f6225SXing Zheng #define SRST_P_HDCP_NOC 245 637f35f6225SXing Zheng #define SRST_P_HDCP 246 638f35f6225SXing Zheng #define SRST_P_HDMI_CTRL 247 639f35f6225SXing Zheng #define SRST_P_DP_CTRL 248 640f35f6225SXing Zheng #define SRST_S_DP_CTRL 249 641f35f6225SXing Zheng #define SRST_C_DP_CTRL 250 642f35f6225SXing Zheng #define SRST_P_MIPI_DSI0 251 643f35f6225SXing Zheng #define SRST_P_MIPI_DSI1 252 644f35f6225SXing Zheng #define SRST_DP_CORE 253 645f35f6225SXing Zheng #define SRST_DP_I2S 254 646f35f6225SXing Zheng 647f35f6225SXing Zheng /* cru_softrst_con16 */ 648f35f6225SXing Zheng #define SRST_GASKET 256 649f35f6225SXing Zheng #define SRST_VIO_GRF 258 650f35f6225SXing Zheng #define SRST_DPTX_SPDIF_REC 259 651f35f6225SXing Zheng #define SRST_HDMI_CTRL 260 652f35f6225SXing Zheng #define SRST_HDCP_CTRL 261 653f35f6225SXing Zheng #define SRST_A_ISP0_NOC 262 654f35f6225SXing Zheng #define SRST_A_ISP1_NOC 263 655f35f6225SXing Zheng #define SRST_H_ISP0_NOC 266 656f35f6225SXing Zheng #define SRST_H_ISP1_NOC 267 657f35f6225SXing Zheng #define SRST_H_ISP0 268 658f35f6225SXing Zheng #define SRST_H_ISP1 269 659f35f6225SXing Zheng #define SRST_ISP0 270 660f35f6225SXing Zheng #define SRST_ISP1 271 661f35f6225SXing Zheng 662f35f6225SXing Zheng /* cru_softrst_con17 */ 663f35f6225SXing Zheng #define SRST_A_VOP0_NOC 272 664f35f6225SXing Zheng #define SRST_A_VOP1_NOC 273 665f35f6225SXing Zheng #define SRST_A_VOP0 274 666f35f6225SXing Zheng #define SRST_A_VOP1 275 667f35f6225SXing Zheng #define SRST_H_VOP0_NOC 276 668f35f6225SXing Zheng #define SRST_H_VOP1_NOC 277 669f35f6225SXing Zheng #define SRST_H_VOP0 278 670f35f6225SXing Zheng #define SRST_H_VOP1 279 671f35f6225SXing Zheng #define SRST_D_VOP0 280 672f35f6225SXing Zheng #define SRST_D_VOP1 281 673f35f6225SXing Zheng #define SRST_VOP0_PWM 282 674f35f6225SXing Zheng #define SRST_VOP1_PWM 283 675f35f6225SXing Zheng #define SRST_P_EDP_NOC 284 676f35f6225SXing Zheng #define SRST_P_EDP_CTRL 285 677f35f6225SXing Zheng 678f35f6225SXing Zheng /* cru_softrst_con18 */ 679f73b5042SXing Zheng #define SRST_A_GPU 288 680f35f6225SXing Zheng #define SRST_A_GPU_NOC 289 681f35f6225SXing Zheng #define SRST_A_GPU_GRF 290 682f35f6225SXing Zheng #define SRST_PVTM_GPU 291 683f35f6225SXing Zheng #define SRST_A_USB3_NOC 292 684f35f6225SXing Zheng #define SRST_A_USB3_OTG0 293 685f35f6225SXing Zheng #define SRST_A_USB3_OTG1 294 686f35f6225SXing Zheng #define SRST_A_USB3_GRF 295 687f35f6225SXing Zheng #define SRST_PMU 296 688f35f6225SXing Zheng 689f35f6225SXing Zheng /* cru_softrst_con19 */ 690f35f6225SXing Zheng #define SRST_P_TIMER0_5 304 691f35f6225SXing Zheng #define SRST_TIMER0 305 692f35f6225SXing Zheng #define SRST_TIMER1 306 693f35f6225SXing Zheng #define SRST_TIMER2 307 694f35f6225SXing Zheng #define SRST_TIMER3 308 695f35f6225SXing Zheng #define SRST_TIMER4 309 696f35f6225SXing Zheng #define SRST_TIMER5 310 697f35f6225SXing Zheng #define SRST_P_TIMER6_11 311 698f35f6225SXing Zheng #define SRST_TIMER6 312 699f35f6225SXing Zheng #define SRST_TIMER7 313 700f35f6225SXing Zheng #define SRST_TIMER8 314 701f35f6225SXing Zheng #define SRST_TIMER9 315 702f35f6225SXing Zheng #define SRST_TIMER10 316 703f35f6225SXing Zheng #define SRST_TIMER11 317 704f35f6225SXing Zheng #define SRST_P_INTR_ARB_PMU 318 705f35f6225SXing Zheng #define SRST_P_ALIVE_SGRF 319 706f35f6225SXing Zheng 707f35f6225SXing Zheng /* cru_softrst_con20 */ 708f35f6225SXing Zheng #define SRST_P_GPIO2 320 709f35f6225SXing Zheng #define SRST_P_GPIO3 321 710f35f6225SXing Zheng #define SRST_P_GPIO4 322 711f35f6225SXing Zheng #define SRST_P_GRF 323 712f35f6225SXing Zheng #define SRST_P_ALIVE_NOC 324 713f35f6225SXing Zheng #define SRST_P_WDT0 325 714f35f6225SXing Zheng #define SRST_P_WDT1 326 715f35f6225SXing Zheng #define SRST_P_INTR_ARB 327 716f35f6225SXing Zheng #define SRST_P_UPHY0_DPTX 328 717f35f6225SXing Zheng #define SRST_P_UPHY0_APB 330 718f35f6225SXing Zheng #define SRST_P_UPHY0_TCPHY 332 719f35f6225SXing Zheng #define SRST_P_UPHY1_TCPHY 333 720f35f6225SXing Zheng #define SRST_P_UPHY0_TCPDCTRL 334 721f35f6225SXing Zheng #define SRST_P_UPHY1_TCPDCTRL 335 722f35f6225SXing Zheng 723f35f6225SXing Zheng /* pmu soft-reset indices */ 724f35f6225SXing Zheng 725f35f6225SXing Zheng /* pmu_cru_softrst_con0 */ 726f35f6225SXing Zheng #define SRST_P_NOC 0 727f35f6225SXing Zheng #define SRST_P_INTMEM 1 728f35f6225SXing Zheng #define SRST_H_CM0S 2 729f35f6225SXing Zheng #define SRST_H_CM0S_NOC 3 730f35f6225SXing Zheng #define SRST_DBG_CM0S 4 731f35f6225SXing Zheng #define SRST_PO_CM0S 5 732f35f6225SXing Zheng #define SRST_P_SPI6 6 733f35f6225SXing Zheng #define SRST_SPI6 7 734f35f6225SXing Zheng #define SRST_P_TIMER_0_1 8 735f35f6225SXing Zheng #define SRST_P_TIMER_0 9 736f35f6225SXing Zheng #define SRST_P_TIMER_1 10 737f35f6225SXing Zheng #define SRST_P_UART4 11 738f35f6225SXing Zheng #define SRST_UART4 12 739f35f6225SXing Zheng #define SRST_P_WDT 13 740f35f6225SXing Zheng 741f35f6225SXing Zheng /* pmu_cru_softrst_con1 */ 742f35f6225SXing Zheng #define SRST_P_I2C6 16 743f35f6225SXing Zheng #define SRST_P_I2C7 17 744f35f6225SXing Zheng #define SRST_P_I2C8 18 745f35f6225SXing Zheng #define SRST_P_MAILBOX 19 746f35f6225SXing Zheng #define SRST_P_RKPWM 20 747f35f6225SXing Zheng #define SRST_P_PMUGRF 21 748f35f6225SXing Zheng #define SRST_P_SGRF 22 749f35f6225SXing Zheng #define SRST_P_GPIO0 23 750f35f6225SXing Zheng #define SRST_P_GPIO1 24 751f35f6225SXing Zheng #define SRST_P_CRU 25 752f35f6225SXing Zheng #define SRST_P_INTR 26 753f35f6225SXing Zheng #define SRST_PVTM 27 754f35f6225SXing Zheng #define SRST_I2C6 28 755f35f6225SXing Zheng #define SRST_I2C7 29 756f35f6225SXing Zheng #define SRST_I2C8 30 757f35f6225SXing Zheng 758f35f6225SXing Zheng #endif 759