1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2f35f6225SXing Zheng /* 3f35f6225SXing Zheng * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 4f35f6225SXing Zheng * Author: Xing Zheng <zhengxing@rock-chips.com> 5f35f6225SXing Zheng */ 6f35f6225SXing Zheng 7f35f6225SXing Zheng #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 8f35f6225SXing Zheng #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 9f35f6225SXing Zheng 10f35f6225SXing Zheng /* core clocks */ 11f35f6225SXing Zheng #define PLL_APLLL 1 12f35f6225SXing Zheng #define PLL_APLLB 2 13f35f6225SXing Zheng #define PLL_DPLL 3 14f35f6225SXing Zheng #define PLL_CPLL 4 15f35f6225SXing Zheng #define PLL_GPLL 5 16f35f6225SXing Zheng #define PLL_NPLL 6 17f35f6225SXing Zheng #define PLL_VPLL 7 18f35f6225SXing Zheng #define ARMCLKL 8 19f35f6225SXing Zheng #define ARMCLKB 9 20f35f6225SXing Zheng 21f35f6225SXing Zheng /* sclk gates (special clocks) */ 22f35f6225SXing Zheng #define SCLK_I2C1 65 23f35f6225SXing Zheng #define SCLK_I2C2 66 24f35f6225SXing Zheng #define SCLK_I2C3 67 25f35f6225SXing Zheng #define SCLK_I2C5 68 26f35f6225SXing Zheng #define SCLK_I2C6 69 27f35f6225SXing Zheng #define SCLK_I2C7 70 28f35f6225SXing Zheng #define SCLK_SPI0 71 29f35f6225SXing Zheng #define SCLK_SPI1 72 30f35f6225SXing Zheng #define SCLK_SPI2 73 31f35f6225SXing Zheng #define SCLK_SPI4 74 32f35f6225SXing Zheng #define SCLK_SPI5 75 33f35f6225SXing Zheng #define SCLK_SDMMC 76 34f35f6225SXing Zheng #define SCLK_SDIO 77 35f35f6225SXing Zheng #define SCLK_EMMC 78 36f35f6225SXing Zheng #define SCLK_TSADC 79 37f35f6225SXing Zheng #define SCLK_SARADC 80 38f35f6225SXing Zheng #define SCLK_UART0 81 39f35f6225SXing Zheng #define SCLK_UART1 82 40f35f6225SXing Zheng #define SCLK_UART2 83 41f35f6225SXing Zheng #define SCLK_UART3 84 42f35f6225SXing Zheng #define SCLK_SPDIF_8CH 85 43f35f6225SXing Zheng #define SCLK_I2S0_8CH 86 44f35f6225SXing Zheng #define SCLK_I2S1_8CH 87 45f35f6225SXing Zheng #define SCLK_I2S2_8CH 88 46f35f6225SXing Zheng #define SCLK_I2S_8CH_OUT 89 47f35f6225SXing Zheng #define SCLK_TIMER00 90 48f35f6225SXing Zheng #define SCLK_TIMER01 91 49f35f6225SXing Zheng #define SCLK_TIMER02 92 50f35f6225SXing Zheng #define SCLK_TIMER03 93 51f35f6225SXing Zheng #define SCLK_TIMER04 94 52f35f6225SXing Zheng #define SCLK_TIMER05 95 53f35f6225SXing Zheng #define SCLK_TIMER06 96 54f35f6225SXing Zheng #define SCLK_TIMER07 97 55f35f6225SXing Zheng #define SCLK_TIMER08 98 56f35f6225SXing Zheng #define SCLK_TIMER09 99 57f35f6225SXing Zheng #define SCLK_TIMER10 100 58f35f6225SXing Zheng #define SCLK_TIMER11 101 59f35f6225SXing Zheng #define SCLK_MACREF 102 60f35f6225SXing Zheng #define SCLK_MAC_RX 103 61f35f6225SXing Zheng #define SCLK_MAC_TX 104 62f35f6225SXing Zheng #define SCLK_MAC 105 63f35f6225SXing Zheng #define SCLK_MACREF_OUT 106 64f35f6225SXing Zheng #define SCLK_VOP0_PWM 107 65f35f6225SXing Zheng #define SCLK_VOP1_PWM 108 66003e6eb7SXing Zheng #define SCLK_RGA_CORE 109 67f35f6225SXing Zheng #define SCLK_ISP0 110 68f35f6225SXing Zheng #define SCLK_ISP1 111 69f35f6225SXing Zheng #define SCLK_HDMI_CEC 112 70f35f6225SXing Zheng #define SCLK_HDMI_SFR 113 71f35f6225SXing Zheng #define SCLK_DP_CORE 114 72f35f6225SXing Zheng #define SCLK_PVTM_CORE_L 115 73f35f6225SXing Zheng #define SCLK_PVTM_CORE_B 116 74f35f6225SXing Zheng #define SCLK_PVTM_GPU 117 75f35f6225SXing Zheng #define SCLK_PVTM_DDR 118 76f35f6225SXing Zheng #define SCLK_MIPIDPHY_REF 119 77f35f6225SXing Zheng #define SCLK_MIPIDPHY_CFG 120 78f35f6225SXing Zheng #define SCLK_HSICPHY 121 79f35f6225SXing Zheng #define SCLK_USBPHY480M 122 80f35f6225SXing Zheng #define SCLK_USB2PHY0_REF 123 81f35f6225SXing Zheng #define SCLK_USB2PHY1_REF 124 82f35f6225SXing Zheng #define SCLK_UPHY0_TCPDPHY_REF 125 83f35f6225SXing Zheng #define SCLK_UPHY0_TCPDCORE 126 84f35f6225SXing Zheng #define SCLK_UPHY1_TCPDPHY_REF 127 85f35f6225SXing Zheng #define SCLK_UPHY1_TCPDCORE 128 86f35f6225SXing Zheng #define SCLK_USB3OTG0_REF 129 87f35f6225SXing Zheng #define SCLK_USB3OTG1_REF 130 88f35f6225SXing Zheng #define SCLK_USB3OTG0_SUSPEND 131 89f35f6225SXing Zheng #define SCLK_USB3OTG1_SUSPEND 132 90f35f6225SXing Zheng #define SCLK_CRYPTO0 133 91f35f6225SXing Zheng #define SCLK_CRYPTO1 134 92f35f6225SXing Zheng #define SCLK_CCI_TRACE 135 93f35f6225SXing Zheng #define SCLK_CS 136 94f35f6225SXing Zheng #define SCLK_CIF_OUT 137 95f35f6225SXing Zheng #define SCLK_PCIEPHY_REF 138 96f35f6225SXing Zheng #define SCLK_PCIE_CORE 139 97f35f6225SXing Zheng #define SCLK_M0_PERILP 140 98f35f6225SXing Zheng #define SCLK_M0_PERILP_DEC 141 99f35f6225SXing Zheng #define SCLK_CM0S 142 100f35f6225SXing Zheng #define SCLK_DBG_NOC 143 101f35f6225SXing Zheng #define SCLK_DBG_PD_CORE_B 144 102f35f6225SXing Zheng #define SCLK_DBG_PD_CORE_L 145 103f35f6225SXing Zheng #define SCLK_DFIMON0_TIMER 146 104f35f6225SXing Zheng #define SCLK_DFIMON1_TIMER 147 105f35f6225SXing Zheng #define SCLK_INTMEM0 148 106f35f6225SXing Zheng #define SCLK_INTMEM1 149 107f35f6225SXing Zheng #define SCLK_INTMEM2 150 108f35f6225SXing Zheng #define SCLK_INTMEM3 151 109f35f6225SXing Zheng #define SCLK_INTMEM4 152 110f35f6225SXing Zheng #define SCLK_INTMEM5 153 111f35f6225SXing Zheng #define SCLK_SDMMC_DRV 154 112f35f6225SXing Zheng #define SCLK_SDMMC_SAMPLE 155 113f35f6225SXing Zheng #define SCLK_SDIO_DRV 156 114f35f6225SXing Zheng #define SCLK_SDIO_SAMPLE 157 115f35f6225SXing Zheng #define SCLK_VDU_CORE 158 116f35f6225SXing Zheng #define SCLK_VDU_CA 159 117f35f6225SXing Zheng #define SCLK_PCIE_PM 160 118f35f6225SXing Zheng #define SCLK_SPDIF_REC_DPTX 161 119f35f6225SXing Zheng #define SCLK_DPHY_PLL 162 120f35f6225SXing Zheng #define SCLK_DPHY_TX0_CFG 163 121f35f6225SXing Zheng #define SCLK_DPHY_TX1RX1_CFG 164 122f35f6225SXing Zheng #define SCLK_DPHY_RX0_CFG 165 12355df4584SXing Zheng #define SCLK_RMII_SRC 166 12455df4584SXing Zheng #define SCLK_PCIEPHY_REF100M 167 1257fbdfcd6SLin Huang #define SCLK_DDRC 168 126f22e4359SEddie Cai #define SCLK_TESTCLKOUT1 169 127f22e4359SEddie Cai #define SCLK_TESTCLKOUT2 170 128f35f6225SXing Zheng 129f35f6225SXing Zheng #define DCLK_VOP0 180 130f35f6225SXing Zheng #define DCLK_VOP1 181 131f35f6225SXing Zheng #define DCLK_VOP0_DIV 182 132f35f6225SXing Zheng #define DCLK_VOP1_DIV 183 133f35f6225SXing Zheng #define DCLK_M0_PERILP 184 134e33075dbSYakir Yang #define DCLK_VOP0_FRAC 185 135e33075dbSYakir Yang #define DCLK_VOP1_FRAC 186 136f35f6225SXing Zheng 137f35f6225SXing Zheng #define FCLK_CM0S 190 138f35f6225SXing Zheng 139f35f6225SXing Zheng /* aclk gates */ 140f35f6225SXing Zheng #define ACLK_PERIHP 192 141f35f6225SXing Zheng #define ACLK_PERIHP_NOC 193 142f35f6225SXing Zheng #define ACLK_PERILP0 194 143f35f6225SXing Zheng #define ACLK_PERILP0_NOC 195 144f35f6225SXing Zheng #define ACLK_PERF_PCIE 196 145f35f6225SXing Zheng #define ACLK_PCIE 197 146f35f6225SXing Zheng #define ACLK_INTMEM 198 147f35f6225SXing Zheng #define ACLK_TZMA 199 148f35f6225SXing Zheng #define ACLK_DCF 200 149f35f6225SXing Zheng #define ACLK_CCI 201 150f35f6225SXing Zheng #define ACLK_CCI_NOC0 202 151f35f6225SXing Zheng #define ACLK_CCI_NOC1 203 152f35f6225SXing Zheng #define ACLK_CCI_GRF 204 153f35f6225SXing Zheng #define ACLK_CENTER 205 154f35f6225SXing Zheng #define ACLK_CENTER_MAIN_NOC 206 155f35f6225SXing Zheng #define ACLK_CENTER_PERI_NOC 207 156f35f6225SXing Zheng #define ACLK_GPU 208 157f35f6225SXing Zheng #define ACLK_PERF_GPU 209 158f35f6225SXing Zheng #define ACLK_GPU_GRF 210 159f35f6225SXing Zheng #define ACLK_DMAC0_PERILP 211 160f35f6225SXing Zheng #define ACLK_DMAC1_PERILP 212 161f35f6225SXing Zheng #define ACLK_GMAC 213 162f35f6225SXing Zheng #define ACLK_GMAC_NOC 214 163f35f6225SXing Zheng #define ACLK_PERF_GMAC 215 164f35f6225SXing Zheng #define ACLK_VOP0_NOC 216 165f35f6225SXing Zheng #define ACLK_VOP0 217 166f35f6225SXing Zheng #define ACLK_VOP1_NOC 218 167f35f6225SXing Zheng #define ACLK_VOP1 219 168f35f6225SXing Zheng #define ACLK_RGA 220 169f35f6225SXing Zheng #define ACLK_RGA_NOC 221 170f35f6225SXing Zheng #define ACLK_HDCP 222 171f35f6225SXing Zheng #define ACLK_HDCP_NOC 223 172f35f6225SXing Zheng #define ACLK_HDCP22 224 173f35f6225SXing Zheng #define ACLK_IEP 225 174f35f6225SXing Zheng #define ACLK_IEP_NOC 226 175f35f6225SXing Zheng #define ACLK_VIO 227 176f35f6225SXing Zheng #define ACLK_VIO_NOC 228 177f35f6225SXing Zheng #define ACLK_ISP0 229 178f35f6225SXing Zheng #define ACLK_ISP1 230 179f35f6225SXing Zheng #define ACLK_ISP0_NOC 231 180f35f6225SXing Zheng #define ACLK_ISP1_NOC 232 181f35f6225SXing Zheng #define ACLK_ISP0_WRAPPER 233 182f35f6225SXing Zheng #define ACLK_ISP1_WRAPPER 234 183f35f6225SXing Zheng #define ACLK_VCODEC 235 184f35f6225SXing Zheng #define ACLK_VCODEC_NOC 236 185f35f6225SXing Zheng #define ACLK_VDU 237 186f35f6225SXing Zheng #define ACLK_VDU_NOC 238 187f35f6225SXing Zheng #define ACLK_PERI 239 188f35f6225SXing Zheng #define ACLK_EMMC 240 189f35f6225SXing Zheng #define ACLK_EMMC_CORE 241 190f35f6225SXing Zheng #define ACLK_EMMC_NOC 242 191f35f6225SXing Zheng #define ACLK_EMMC_GRF 243 192f35f6225SXing Zheng #define ACLK_USB3 244 193f35f6225SXing Zheng #define ACLK_USB3_NOC 245 194f35f6225SXing Zheng #define ACLK_USB3OTG0 246 195f35f6225SXing Zheng #define ACLK_USB3OTG1 247 196f35f6225SXing Zheng #define ACLK_USB3_RKSOC_AXI_PERF 248 197f35f6225SXing Zheng #define ACLK_USB3_GRF 249 198f35f6225SXing Zheng #define ACLK_GIC 250 199f35f6225SXing Zheng #define ACLK_GIC_NOC 251 200f35f6225SXing Zheng #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 201f35f6225SXing Zheng #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 202f35f6225SXing Zheng #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 203f35f6225SXing Zheng #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 204f35f6225SXing Zheng #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 205f35f6225SXing Zheng #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 206f35f6225SXing Zheng #define ACLK_ADB400M_PD_CORE_L 258 207f35f6225SXing Zheng #define ACLK_ADB400M_PD_CORE_B 259 208f35f6225SXing Zheng #define ACLK_PERF_CORE_L 260 209f35f6225SXing Zheng #define ACLK_PERF_CORE_B 261 210f35f6225SXing Zheng #define ACLK_GIC_PRE 262 211f35f6225SXing Zheng #define ACLK_VOP0_PRE 263 212f35f6225SXing Zheng #define ACLK_VOP1_PRE 264 213f35f6225SXing Zheng 214f35f6225SXing Zheng /* pclk gates */ 215f35f6225SXing Zheng #define PCLK_PERIHP 320 216f35f6225SXing Zheng #define PCLK_PERIHP_NOC 321 217f35f6225SXing Zheng #define PCLK_PERILP0 322 218f35f6225SXing Zheng #define PCLK_PERILP1 323 219f35f6225SXing Zheng #define PCLK_PERILP1_NOC 324 220f35f6225SXing Zheng #define PCLK_PERILP_SGRF 325 221f35f6225SXing Zheng #define PCLK_PERIHP_GRF 326 222f35f6225SXing Zheng #define PCLK_PCIE 327 223f35f6225SXing Zheng #define PCLK_SGRF 328 224f35f6225SXing Zheng #define PCLK_INTR_ARB 329 225f35f6225SXing Zheng #define PCLK_CENTER_MAIN_NOC 330 226f35f6225SXing Zheng #define PCLK_CIC 331 227f35f6225SXing Zheng #define PCLK_COREDBG_B 332 228f35f6225SXing Zheng #define PCLK_COREDBG_L 333 229f35f6225SXing Zheng #define PCLK_DBG_CXCS_PD_CORE_B 334 230f35f6225SXing Zheng #define PCLK_DCF 335 231f35f6225SXing Zheng #define PCLK_GPIO2 336 232f35f6225SXing Zheng #define PCLK_GPIO3 337 233f35f6225SXing Zheng #define PCLK_GPIO4 338 234f35f6225SXing Zheng #define PCLK_GRF 339 235f35f6225SXing Zheng #define PCLK_HSICPHY 340 236f35f6225SXing Zheng #define PCLK_I2C1 341 237f35f6225SXing Zheng #define PCLK_I2C2 342 238f35f6225SXing Zheng #define PCLK_I2C3 343 239f35f6225SXing Zheng #define PCLK_I2C5 344 240f35f6225SXing Zheng #define PCLK_I2C6 345 241f35f6225SXing Zheng #define PCLK_I2C7 346 242f35f6225SXing Zheng #define PCLK_SPI0 347 243f35f6225SXing Zheng #define PCLK_SPI1 348 244f35f6225SXing Zheng #define PCLK_SPI2 349 245f35f6225SXing Zheng #define PCLK_SPI4 350 246f35f6225SXing Zheng #define PCLK_SPI5 351 247f35f6225SXing Zheng #define PCLK_UART0 352 248f35f6225SXing Zheng #define PCLK_UART1 353 249f35f6225SXing Zheng #define PCLK_UART2 354 250f35f6225SXing Zheng #define PCLK_UART3 355 251f35f6225SXing Zheng #define PCLK_TSADC 356 252f35f6225SXing Zheng #define PCLK_SARADC 357 253f35f6225SXing Zheng #define PCLK_GMAC 358 254f35f6225SXing Zheng #define PCLK_GMAC_NOC 359 255f35f6225SXing Zheng #define PCLK_TIMER0 360 256f35f6225SXing Zheng #define PCLK_TIMER1 361 257f35f6225SXing Zheng #define PCLK_EDP 362 258f35f6225SXing Zheng #define PCLK_EDP_NOC 363 259f35f6225SXing Zheng #define PCLK_EDP_CTRL 364 260f35f6225SXing Zheng #define PCLK_VIO 365 261f35f6225SXing Zheng #define PCLK_VIO_NOC 366 262f35f6225SXing Zheng #define PCLK_VIO_GRF 367 263f35f6225SXing Zheng #define PCLK_MIPI_DSI0 368 264f35f6225SXing Zheng #define PCLK_MIPI_DSI1 369 265f35f6225SXing Zheng #define PCLK_HDCP 370 266f35f6225SXing Zheng #define PCLK_HDCP_NOC 371 267f35f6225SXing Zheng #define PCLK_HDMI_CTRL 372 268f35f6225SXing Zheng #define PCLK_DP_CTRL 373 269f35f6225SXing Zheng #define PCLK_HDCP22 374 270f35f6225SXing Zheng #define PCLK_GASKET 375 271f35f6225SXing Zheng #define PCLK_DDR 376 272f35f6225SXing Zheng #define PCLK_DDR_MON 377 273f35f6225SXing Zheng #define PCLK_DDR_SGRF 378 274f35f6225SXing Zheng #define PCLK_ISP1_WRAPPER 379 275f35f6225SXing Zheng #define PCLK_WDT 380 276f35f6225SXing Zheng #define PCLK_EFUSE1024NS 381 277f35f6225SXing Zheng #define PCLK_EFUSE1024S 382 278f35f6225SXing Zheng #define PCLK_PMU_INTR_ARB 383 279f35f6225SXing Zheng #define PCLK_MAILBOX0 384 280f35f6225SXing Zheng #define PCLK_USBPHY_MUX_G 385 281f35f6225SXing Zheng #define PCLK_UPHY0_TCPHY_G 386 282f35f6225SXing Zheng #define PCLK_UPHY0_TCPD_G 387 283f35f6225SXing Zheng #define PCLK_UPHY1_TCPHY_G 388 284f35f6225SXing Zheng #define PCLK_UPHY1_TCPD_G 389 285f35f6225SXing Zheng #define PCLK_ALIVE 390 286f35f6225SXing Zheng 287f35f6225SXing Zheng /* hclk gates */ 288f35f6225SXing Zheng #define HCLK_PERIHP 448 289f35f6225SXing Zheng #define HCLK_PERILP0 449 290f35f6225SXing Zheng #define HCLK_PERILP1 450 291f35f6225SXing Zheng #define HCLK_PERILP0_NOC 451 292f35f6225SXing Zheng #define HCLK_PERILP1_NOC 452 293f35f6225SXing Zheng #define HCLK_M0_PERILP 453 294f35f6225SXing Zheng #define HCLK_M0_PERILP_NOC 454 295f35f6225SXing Zheng #define HCLK_AHB1TOM 455 296f35f6225SXing Zheng #define HCLK_HOST0 456 297f35f6225SXing Zheng #define HCLK_HOST0_ARB 457 298f35f6225SXing Zheng #define HCLK_HOST1 458 299f35f6225SXing Zheng #define HCLK_HOST1_ARB 459 300f35f6225SXing Zheng #define HCLK_HSIC 460 301f35f6225SXing Zheng #define HCLK_SD 461 302f35f6225SXing Zheng #define HCLK_SDMMC 462 303f35f6225SXing Zheng #define HCLK_SDMMC_NOC 463 304f35f6225SXing Zheng #define HCLK_M_CRYPTO0 464 305f35f6225SXing Zheng #define HCLK_M_CRYPTO1 465 306f35f6225SXing Zheng #define HCLK_S_CRYPTO0 466 307f35f6225SXing Zheng #define HCLK_S_CRYPTO1 467 308f35f6225SXing Zheng #define HCLK_I2S0_8CH 468 309f35f6225SXing Zheng #define HCLK_I2S1_8CH 469 310f35f6225SXing Zheng #define HCLK_I2S2_8CH 470 311f35f6225SXing Zheng #define HCLK_SPDIF 471 312f35f6225SXing Zheng #define HCLK_VOP0_NOC 472 313f35f6225SXing Zheng #define HCLK_VOP0 473 314f35f6225SXing Zheng #define HCLK_VOP1_NOC 474 315f35f6225SXing Zheng #define HCLK_VOP1 475 316f35f6225SXing Zheng #define HCLK_ROM 476 317f35f6225SXing Zheng #define HCLK_IEP 477 318f35f6225SXing Zheng #define HCLK_IEP_NOC 478 319f35f6225SXing Zheng #define HCLK_ISP0 479 320f35f6225SXing Zheng #define HCLK_ISP1 480 321f35f6225SXing Zheng #define HCLK_ISP0_NOC 481 322f35f6225SXing Zheng #define HCLK_ISP1_NOC 482 323f35f6225SXing Zheng #define HCLK_ISP0_WRAPPER 483 324f35f6225SXing Zheng #define HCLK_ISP1_WRAPPER 484 325f35f6225SXing Zheng #define HCLK_RGA 485 326f35f6225SXing Zheng #define HCLK_RGA_NOC 486 327f35f6225SXing Zheng #define HCLK_HDCP 487 328f35f6225SXing Zheng #define HCLK_HDCP_NOC 488 329f35f6225SXing Zheng #define HCLK_HDCP22 489 330f35f6225SXing Zheng #define HCLK_VCODEC 490 331f35f6225SXing Zheng #define HCLK_VCODEC_NOC 491 332f35f6225SXing Zheng #define HCLK_VDU 492 333f35f6225SXing Zheng #define HCLK_VDU_NOC 493 334f35f6225SXing Zheng #define HCLK_SDIO 494 335f35f6225SXing Zheng #define HCLK_SDIO_NOC 495 336f35f6225SXing Zheng #define HCLK_SDIOAUDIO_NOC 496 337f35f6225SXing Zheng 338f35f6225SXing Zheng #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 339f35f6225SXing Zheng 340f35f6225SXing Zheng /* pmu-clocks indices */ 341f35f6225SXing Zheng 342f35f6225SXing Zheng #define PLL_PPLL 1 343f35f6225SXing Zheng 344f35f6225SXing Zheng #define SCLK_32K_SUSPEND_PMU 2 345f35f6225SXing Zheng #define SCLK_SPI3_PMU 3 346f35f6225SXing Zheng #define SCLK_TIMER12_PMU 4 347f35f6225SXing Zheng #define SCLK_TIMER13_PMU 5 348f35f6225SXing Zheng #define SCLK_UART4_PMU 6 349f35f6225SXing Zheng #define SCLK_PVTM_PMU 7 350f35f6225SXing Zheng #define SCLK_WIFI_PMU 8 351f35f6225SXing Zheng #define SCLK_I2C0_PMU 9 352f35f6225SXing Zheng #define SCLK_I2C4_PMU 10 353f35f6225SXing Zheng #define SCLK_I2C8_PMU 11 354f35f6225SXing Zheng 355f35f6225SXing Zheng #define PCLK_SRC_PMU 19 356f35f6225SXing Zheng #define PCLK_PMU 20 357f35f6225SXing Zheng #define PCLK_PMUGRF_PMU 21 358f35f6225SXing Zheng #define PCLK_INTMEM1_PMU 22 359f35f6225SXing Zheng #define PCLK_GPIO0_PMU 23 360f35f6225SXing Zheng #define PCLK_GPIO1_PMU 24 361f35f6225SXing Zheng #define PCLK_SGRF_PMU 25 362f35f6225SXing Zheng #define PCLK_NOC_PMU 26 363f35f6225SXing Zheng #define PCLK_I2C0_PMU 27 364f35f6225SXing Zheng #define PCLK_I2C4_PMU 28 365f35f6225SXing Zheng #define PCLK_I2C8_PMU 29 366f35f6225SXing Zheng #define PCLK_RKPWM_PMU 30 367f35f6225SXing Zheng #define PCLK_SPI3_PMU 31 368f35f6225SXing Zheng #define PCLK_TIMER_PMU 32 369f35f6225SXing Zheng #define PCLK_MAILBOX_PMU 33 370f35f6225SXing Zheng #define PCLK_UART4_PMU 34 371f35f6225SXing Zheng #define PCLK_WDT_M0_PMU 35 372f35f6225SXing Zheng 373f35f6225SXing Zheng #define FCLK_CM0S_SRC_PMU 44 374f35f6225SXing Zheng #define FCLK_CM0S_PMU 45 375f35f6225SXing Zheng #define SCLK_CM0S_PMU 46 376f35f6225SXing Zheng #define HCLK_CM0S_PMU 47 377f35f6225SXing Zheng #define DCLK_CM0S_PMU 48 378f35f6225SXing Zheng #define PCLK_INTR_ARB_PMU 49 379f35f6225SXing Zheng #define HCLK_NOC_PMU 50 380f35f6225SXing Zheng 381f35f6225SXing Zheng #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 382f35f6225SXing Zheng 383f35f6225SXing Zheng /* soft-reset indices */ 384f35f6225SXing Zheng 385f35f6225SXing Zheng /* cru_softrst_con0 */ 386f35f6225SXing Zheng #define SRST_CORE_L0 0 387f35f6225SXing Zheng #define SRST_CORE_B0 1 388f35f6225SXing Zheng #define SRST_CORE_PO_L0 2 389f35f6225SXing Zheng #define SRST_CORE_PO_B0 3 390f35f6225SXing Zheng #define SRST_L2_L 4 391f35f6225SXing Zheng #define SRST_L2_B 5 392f35f6225SXing Zheng #define SRST_ADB_L 6 393f35f6225SXing Zheng #define SRST_ADB_B 7 394f35f6225SXing Zheng #define SRST_A_CCI 8 395f35f6225SXing Zheng #define SRST_A_CCIM0_NOC 9 396f35f6225SXing Zheng #define SRST_A_CCIM1_NOC 10 397f35f6225SXing Zheng #define SRST_DBG_NOC 11 398f35f6225SXing Zheng 399f35f6225SXing Zheng /* cru_softrst_con1 */ 400f35f6225SXing Zheng #define SRST_CORE_L0_T 16 401f35f6225SXing Zheng #define SRST_CORE_L1 17 402f35f6225SXing Zheng #define SRST_CORE_L2 18 403f35f6225SXing Zheng #define SRST_CORE_L3 19 404f35f6225SXing Zheng #define SRST_CORE_PO_L0_T 20 405f35f6225SXing Zheng #define SRST_CORE_PO_L1 21 406f35f6225SXing Zheng #define SRST_CORE_PO_L2 22 407f35f6225SXing Zheng #define SRST_CORE_PO_L3 23 408f35f6225SXing Zheng #define SRST_A_ADB400_GIC2COREL 24 409f35f6225SXing Zheng #define SRST_A_ADB400_COREL2GIC 25 410f35f6225SXing Zheng #define SRST_P_DBG_L 26 411f35f6225SXing Zheng #define SRST_L2_L_T 28 412f35f6225SXing Zheng #define SRST_ADB_L_T 29 413f35f6225SXing Zheng #define SRST_A_RKPERF_L 30 414f35f6225SXing Zheng #define SRST_PVTM_CORE_L 31 415f35f6225SXing Zheng 416f35f6225SXing Zheng /* cru_softrst_con2 */ 417f35f6225SXing Zheng #define SRST_CORE_B0_T 32 418f35f6225SXing Zheng #define SRST_CORE_B1 33 419f35f6225SXing Zheng #define SRST_CORE_PO_B0_T 36 420f35f6225SXing Zheng #define SRST_CORE_PO_B1 37 421f35f6225SXing Zheng #define SRST_A_ADB400_GIC2COREB 40 422f35f6225SXing Zheng #define SRST_A_ADB400_COREB2GIC 41 423f35f6225SXing Zheng #define SRST_P_DBG_B 42 424f35f6225SXing Zheng #define SRST_L2_B_T 43 425f35f6225SXing Zheng #define SRST_ADB_B_T 45 426f35f6225SXing Zheng #define SRST_A_RKPERF_B 46 427f35f6225SXing Zheng #define SRST_PVTM_CORE_B 47 428f35f6225SXing Zheng 429f35f6225SXing Zheng /* cru_softrst_con3 */ 430f35f6225SXing Zheng #define SRST_A_CCI_T 50 431f35f6225SXing Zheng #define SRST_A_CCIM0_NOC_T 51 432f35f6225SXing Zheng #define SRST_A_CCIM1_NOC_T 52 433f35f6225SXing Zheng #define SRST_A_ADB400M_PD_CORE_B_T 53 434f35f6225SXing Zheng #define SRST_A_ADB400M_PD_CORE_L_T 54 435f35f6225SXing Zheng #define SRST_DBG_NOC_T 55 436f35f6225SXing Zheng #define SRST_DBG_CXCS 56 437f35f6225SXing Zheng #define SRST_CCI_TRACE 57 438f35f6225SXing Zheng #define SRST_P_CCI_GRF 58 439f35f6225SXing Zheng 440f35f6225SXing Zheng /* cru_softrst_con4 */ 441f35f6225SXing Zheng #define SRST_A_CENTER_MAIN_NOC 64 442f35f6225SXing Zheng #define SRST_A_CENTER_PERI_NOC 65 443f35f6225SXing Zheng #define SRST_P_CENTER_MAIN 66 444f35f6225SXing Zheng #define SRST_P_DDRMON 67 445f35f6225SXing Zheng #define SRST_P_CIC 68 446f35f6225SXing Zheng #define SRST_P_CENTER_SGRF 69 447f35f6225SXing Zheng #define SRST_DDR0_MSCH 70 448f35f6225SXing Zheng #define SRST_DDRCFG0_MSCH 71 449f35f6225SXing Zheng #define SRST_DDR0 72 450f35f6225SXing Zheng #define SRST_DDRPHY0 73 451f35f6225SXing Zheng #define SRST_DDR1_MSCH 74 452f35f6225SXing Zheng #define SRST_DDRCFG1_MSCH 75 453f35f6225SXing Zheng #define SRST_DDR1 76 454f35f6225SXing Zheng #define SRST_DDRPHY1 77 455f35f6225SXing Zheng #define SRST_DDR_CIC 78 456f35f6225SXing Zheng #define SRST_PVTM_DDR 79 457f35f6225SXing Zheng 458f35f6225SXing Zheng /* cru_softrst_con5 */ 459f35f6225SXing Zheng #define SRST_A_VCODEC_NOC 80 460f35f6225SXing Zheng #define SRST_A_VCODEC 81 461f35f6225SXing Zheng #define SRST_H_VCODEC_NOC 82 462f35f6225SXing Zheng #define SRST_H_VCODEC 83 463f35f6225SXing Zheng #define SRST_A_VDU_NOC 88 464f35f6225SXing Zheng #define SRST_A_VDU 89 465f35f6225SXing Zheng #define SRST_H_VDU_NOC 90 466f35f6225SXing Zheng #define SRST_H_VDU 91 467f35f6225SXing Zheng #define SRST_VDU_CORE 92 468f35f6225SXing Zheng #define SRST_VDU_CA 93 469f35f6225SXing Zheng 470f35f6225SXing Zheng /* cru_softrst_con6 */ 471f35f6225SXing Zheng #define SRST_A_IEP_NOC 96 472f35f6225SXing Zheng #define SRST_A_VOP_IEP 97 473f35f6225SXing Zheng #define SRST_A_IEP 98 474f35f6225SXing Zheng #define SRST_H_IEP_NOC 99 475f35f6225SXing Zheng #define SRST_H_IEP 100 476f35f6225SXing Zheng #define SRST_A_RGA_NOC 102 477f35f6225SXing Zheng #define SRST_A_RGA 103 478f35f6225SXing Zheng #define SRST_H_RGA_NOC 104 479f35f6225SXing Zheng #define SRST_H_RGA 105 480f35f6225SXing Zheng #define SRST_RGA_CORE 106 481f35f6225SXing Zheng #define SRST_EMMC_NOC 108 482f35f6225SXing Zheng #define SRST_EMMC 109 483f35f6225SXing Zheng #define SRST_EMMC_GRF 110 484f35f6225SXing Zheng 485f35f6225SXing Zheng /* cru_softrst_con7 */ 486f35f6225SXing Zheng #define SRST_A_PERIHP_NOC 112 487f35f6225SXing Zheng #define SRST_P_PERIHP_GRF 113 488f35f6225SXing Zheng #define SRST_H_PERIHP_NOC 114 489f35f6225SXing Zheng #define SRST_USBHOST0 115 490f35f6225SXing Zheng #define SRST_HOSTC0_AUX 116 491f35f6225SXing Zheng #define SRST_HOST0_ARB 117 492f35f6225SXing Zheng #define SRST_USBHOST1 118 493f35f6225SXing Zheng #define SRST_HOSTC1_AUX 119 494f35f6225SXing Zheng #define SRST_HOST1_ARB 120 495f35f6225SXing Zheng #define SRST_SDIO0 121 496f35f6225SXing Zheng #define SRST_SDMMC 122 497f35f6225SXing Zheng #define SRST_HSIC 123 498f35f6225SXing Zheng #define SRST_HSIC_AUX 124 499f35f6225SXing Zheng #define SRST_AHB1TOM 125 500f35f6225SXing Zheng #define SRST_P_PERIHP_NOC 126 501f35f6225SXing Zheng #define SRST_HSICPHY 127 502f35f6225SXing Zheng 503f35f6225SXing Zheng /* cru_softrst_con8 */ 504f35f6225SXing Zheng #define SRST_A_PCIE 128 505f35f6225SXing Zheng #define SRST_P_PCIE 129 506f35f6225SXing Zheng #define SRST_PCIE_CORE 130 507f35f6225SXing Zheng #define SRST_PCIE_MGMT 131 508f35f6225SXing Zheng #define SRST_PCIE_MGMT_STICKY 132 509f35f6225SXing Zheng #define SRST_PCIE_PIPE 133 510f35f6225SXing Zheng #define SRST_PCIE_PM 134 511f35f6225SXing Zheng #define SRST_PCIEPHY 135 512f35f6225SXing Zheng #define SRST_A_GMAC_NOC 136 513f35f6225SXing Zheng #define SRST_A_GMAC 137 514f35f6225SXing Zheng #define SRST_P_GMAC_NOC 138 515f35f6225SXing Zheng #define SRST_P_GMAC_GRF 140 516f35f6225SXing Zheng #define SRST_HSICPHY_POR 142 517f35f6225SXing Zheng #define SRST_HSICPHY_UTMI 143 518f35f6225SXing Zheng 519f35f6225SXing Zheng /* cru_softrst_con9 */ 520f35f6225SXing Zheng #define SRST_USB2PHY0_POR 144 521f35f6225SXing Zheng #define SRST_USB2PHY0_UTMI_PORT0 145 522f35f6225SXing Zheng #define SRST_USB2PHY0_UTMI_PORT1 146 523f35f6225SXing Zheng #define SRST_USB2PHY0_EHCIPHY 147 524f35f6225SXing Zheng #define SRST_UPHY0_PIPE_L00 148 525f35f6225SXing Zheng #define SRST_UPHY0 149 526f35f6225SXing Zheng #define SRST_UPHY0_TCPDPWRUP 150 527f35f6225SXing Zheng #define SRST_USB2PHY1_POR 152 528f35f6225SXing Zheng #define SRST_USB2PHY1_UTMI_PORT0 153 529f35f6225SXing Zheng #define SRST_USB2PHY1_UTMI_PORT1 154 530f35f6225SXing Zheng #define SRST_USB2PHY1_EHCIPHY 155 531f35f6225SXing Zheng #define SRST_UPHY1_PIPE_L00 156 532f35f6225SXing Zheng #define SRST_UPHY1 157 533f35f6225SXing Zheng #define SRST_UPHY1_TCPDPWRUP 158 534f35f6225SXing Zheng 535f35f6225SXing Zheng /* cru_softrst_con10 */ 536f35f6225SXing Zheng #define SRST_A_PERILP0_NOC 160 537f35f6225SXing Zheng #define SRST_A_DCF 161 538f35f6225SXing Zheng #define SRST_GIC500 162 539f35f6225SXing Zheng #define SRST_DMAC0_PERILP0 163 540f35f6225SXing Zheng #define SRST_DMAC1_PERILP0 164 541f35f6225SXing Zheng #define SRST_TZMA 165 542f35f6225SXing Zheng #define SRST_INTMEM 166 543f35f6225SXing Zheng #define SRST_ADB400_MST0 167 544f35f6225SXing Zheng #define SRST_ADB400_MST1 168 545f35f6225SXing Zheng #define SRST_ADB400_SLV0 169 546f35f6225SXing Zheng #define SRST_ADB400_SLV1 170 547f35f6225SXing Zheng #define SRST_H_PERILP0 171 548f35f6225SXing Zheng #define SRST_H_PERILP0_NOC 172 549f35f6225SXing Zheng #define SRST_ROM 173 550*b136468aSCorentin Labbe #define SRST_CRYPTO0_S 174 551*b136468aSCorentin Labbe #define SRST_CRYPTO0_M 175 552f35f6225SXing Zheng 553f35f6225SXing Zheng /* cru_softrst_con11 */ 554f35f6225SXing Zheng #define SRST_P_DCF 176 555f35f6225SXing Zheng #define SRST_CM0S_NOC 177 556f35f6225SXing Zheng #define SRST_CM0S 178 557f35f6225SXing Zheng #define SRST_CM0S_DBG 179 558f35f6225SXing Zheng #define SRST_CM0S_PO 180 559*b136468aSCorentin Labbe #define SRST_CRYPTO0 181 560f35f6225SXing Zheng #define SRST_P_PERILP1_SGRF 182 561f35f6225SXing Zheng #define SRST_P_PERILP1_GRF 183 562f35f6225SXing Zheng #define SRST_CRYPTO1_S 184 563f35f6225SXing Zheng #define SRST_CRYPTO1_M 185 564f35f6225SXing Zheng #define SRST_CRYPTO1 186 565f35f6225SXing Zheng #define SRST_GIC_NOC 188 566f35f6225SXing Zheng #define SRST_SD_NOC 189 567f35f6225SXing Zheng #define SRST_SDIOAUDIO_BRG 190 568f35f6225SXing Zheng 569f35f6225SXing Zheng /* cru_softrst_con12 */ 570f35f6225SXing Zheng #define SRST_H_PERILP1 192 571f35f6225SXing Zheng #define SRST_H_PERILP1_NOC 193 572f35f6225SXing Zheng #define SRST_H_I2S0_8CH 194 573f35f6225SXing Zheng #define SRST_H_I2S1_8CH 195 574f35f6225SXing Zheng #define SRST_H_I2S2_8CH 196 575f35f6225SXing Zheng #define SRST_H_SPDIF_8CH 197 576f35f6225SXing Zheng #define SRST_P_PERILP1_NOC 198 577f35f6225SXing Zheng #define SRST_P_EFUSE_1024 199 578f35f6225SXing Zheng #define SRST_P_EFUSE_1024S 200 579f35f6225SXing Zheng #define SRST_P_I2C0 201 580f35f6225SXing Zheng #define SRST_P_I2C1 202 581f35f6225SXing Zheng #define SRST_P_I2C2 203 582f35f6225SXing Zheng #define SRST_P_I2C3 204 583f35f6225SXing Zheng #define SRST_P_I2C4 205 584f35f6225SXing Zheng #define SRST_P_I2C5 206 585f35f6225SXing Zheng #define SRST_P_MAILBOX0 207 586f35f6225SXing Zheng 587f35f6225SXing Zheng /* cru_softrst_con13 */ 588f35f6225SXing Zheng #define SRST_P_UART0 208 589f35f6225SXing Zheng #define SRST_P_UART1 209 590f35f6225SXing Zheng #define SRST_P_UART2 210 591f35f6225SXing Zheng #define SRST_P_UART3 211 592f35f6225SXing Zheng #define SRST_P_SARADC 212 593f35f6225SXing Zheng #define SRST_P_TSADC 213 594f35f6225SXing Zheng #define SRST_P_SPI0 214 595f35f6225SXing Zheng #define SRST_P_SPI1 215 596f35f6225SXing Zheng #define SRST_P_SPI2 216 597f35f6225SXing Zheng #define SRST_P_SPI3 217 598f35f6225SXing Zheng #define SRST_P_SPI4 218 599f35f6225SXing Zheng #define SRST_SPI0 219 600f35f6225SXing Zheng #define SRST_SPI1 220 601f35f6225SXing Zheng #define SRST_SPI2 221 602f35f6225SXing Zheng #define SRST_SPI3 222 603f35f6225SXing Zheng #define SRST_SPI4 223 604f35f6225SXing Zheng 605f35f6225SXing Zheng /* cru_softrst_con14 */ 606f35f6225SXing Zheng #define SRST_I2S0_8CH 224 607f35f6225SXing Zheng #define SRST_I2S1_8CH 225 608f35f6225SXing Zheng #define SRST_I2S2_8CH 226 609f35f6225SXing Zheng #define SRST_SPDIF_8CH 227 610f35f6225SXing Zheng #define SRST_UART0 228 611f35f6225SXing Zheng #define SRST_UART1 229 612f35f6225SXing Zheng #define SRST_UART2 230 613f35f6225SXing Zheng #define SRST_UART3 231 614f35f6225SXing Zheng #define SRST_TSADC 232 615f35f6225SXing Zheng #define SRST_I2C0 233 616f35f6225SXing Zheng #define SRST_I2C1 234 617f35f6225SXing Zheng #define SRST_I2C2 235 618f35f6225SXing Zheng #define SRST_I2C3 236 619f35f6225SXing Zheng #define SRST_I2C4 237 620f35f6225SXing Zheng #define SRST_I2C5 238 621f35f6225SXing Zheng #define SRST_SDIOAUDIO_NOC 239 622f35f6225SXing Zheng 623f35f6225SXing Zheng /* cru_softrst_con15 */ 624f35f6225SXing Zheng #define SRST_A_VIO_NOC 240 625f35f6225SXing Zheng #define SRST_A_HDCP_NOC 241 626f35f6225SXing Zheng #define SRST_A_HDCP 242 627f35f6225SXing Zheng #define SRST_H_HDCP_NOC 243 628f35f6225SXing Zheng #define SRST_H_HDCP 244 629f35f6225SXing Zheng #define SRST_P_HDCP_NOC 245 630f35f6225SXing Zheng #define SRST_P_HDCP 246 631f35f6225SXing Zheng #define SRST_P_HDMI_CTRL 247 632f35f6225SXing Zheng #define SRST_P_DP_CTRL 248 633f35f6225SXing Zheng #define SRST_S_DP_CTRL 249 634f35f6225SXing Zheng #define SRST_C_DP_CTRL 250 635f35f6225SXing Zheng #define SRST_P_MIPI_DSI0 251 636f35f6225SXing Zheng #define SRST_P_MIPI_DSI1 252 637f35f6225SXing Zheng #define SRST_DP_CORE 253 638f35f6225SXing Zheng #define SRST_DP_I2S 254 639f35f6225SXing Zheng 640f35f6225SXing Zheng /* cru_softrst_con16 */ 641f35f6225SXing Zheng #define SRST_GASKET 256 642f35f6225SXing Zheng #define SRST_VIO_GRF 258 643f35f6225SXing Zheng #define SRST_DPTX_SPDIF_REC 259 644f35f6225SXing Zheng #define SRST_HDMI_CTRL 260 645f35f6225SXing Zheng #define SRST_HDCP_CTRL 261 646f35f6225SXing Zheng #define SRST_A_ISP0_NOC 262 647f35f6225SXing Zheng #define SRST_A_ISP1_NOC 263 648f35f6225SXing Zheng #define SRST_H_ISP0_NOC 266 649f35f6225SXing Zheng #define SRST_H_ISP1_NOC 267 650f35f6225SXing Zheng #define SRST_H_ISP0 268 651f35f6225SXing Zheng #define SRST_H_ISP1 269 652f35f6225SXing Zheng #define SRST_ISP0 270 653f35f6225SXing Zheng #define SRST_ISP1 271 654f35f6225SXing Zheng 655f35f6225SXing Zheng /* cru_softrst_con17 */ 656f35f6225SXing Zheng #define SRST_A_VOP0_NOC 272 657f35f6225SXing Zheng #define SRST_A_VOP1_NOC 273 658f35f6225SXing Zheng #define SRST_A_VOP0 274 659f35f6225SXing Zheng #define SRST_A_VOP1 275 660f35f6225SXing Zheng #define SRST_H_VOP0_NOC 276 661f35f6225SXing Zheng #define SRST_H_VOP1_NOC 277 662f35f6225SXing Zheng #define SRST_H_VOP0 278 663f35f6225SXing Zheng #define SRST_H_VOP1 279 664f35f6225SXing Zheng #define SRST_D_VOP0 280 665f35f6225SXing Zheng #define SRST_D_VOP1 281 666f35f6225SXing Zheng #define SRST_VOP0_PWM 282 667f35f6225SXing Zheng #define SRST_VOP1_PWM 283 668f35f6225SXing Zheng #define SRST_P_EDP_NOC 284 669f35f6225SXing Zheng #define SRST_P_EDP_CTRL 285 670f35f6225SXing Zheng 671f35f6225SXing Zheng /* cru_softrst_con18 */ 672f73b5042SXing Zheng #define SRST_A_GPU 288 673f35f6225SXing Zheng #define SRST_A_GPU_NOC 289 674f35f6225SXing Zheng #define SRST_A_GPU_GRF 290 675f35f6225SXing Zheng #define SRST_PVTM_GPU 291 676f35f6225SXing Zheng #define SRST_A_USB3_NOC 292 677f35f6225SXing Zheng #define SRST_A_USB3_OTG0 293 678f35f6225SXing Zheng #define SRST_A_USB3_OTG1 294 679f35f6225SXing Zheng #define SRST_A_USB3_GRF 295 680f35f6225SXing Zheng #define SRST_PMU 296 681f35f6225SXing Zheng 682f35f6225SXing Zheng /* cru_softrst_con19 */ 683f35f6225SXing Zheng #define SRST_P_TIMER0_5 304 684f35f6225SXing Zheng #define SRST_TIMER0 305 685f35f6225SXing Zheng #define SRST_TIMER1 306 686f35f6225SXing Zheng #define SRST_TIMER2 307 687f35f6225SXing Zheng #define SRST_TIMER3 308 688f35f6225SXing Zheng #define SRST_TIMER4 309 689f35f6225SXing Zheng #define SRST_TIMER5 310 690f35f6225SXing Zheng #define SRST_P_TIMER6_11 311 691f35f6225SXing Zheng #define SRST_TIMER6 312 692f35f6225SXing Zheng #define SRST_TIMER7 313 693f35f6225SXing Zheng #define SRST_TIMER8 314 694f35f6225SXing Zheng #define SRST_TIMER9 315 695f35f6225SXing Zheng #define SRST_TIMER10 316 696f35f6225SXing Zheng #define SRST_TIMER11 317 697f35f6225SXing Zheng #define SRST_P_INTR_ARB_PMU 318 698f35f6225SXing Zheng #define SRST_P_ALIVE_SGRF 319 699f35f6225SXing Zheng 700f35f6225SXing Zheng /* cru_softrst_con20 */ 701f35f6225SXing Zheng #define SRST_P_GPIO2 320 702f35f6225SXing Zheng #define SRST_P_GPIO3 321 703f35f6225SXing Zheng #define SRST_P_GPIO4 322 704f35f6225SXing Zheng #define SRST_P_GRF 323 705f35f6225SXing Zheng #define SRST_P_ALIVE_NOC 324 706f35f6225SXing Zheng #define SRST_P_WDT0 325 707f35f6225SXing Zheng #define SRST_P_WDT1 326 708f35f6225SXing Zheng #define SRST_P_INTR_ARB 327 709f35f6225SXing Zheng #define SRST_P_UPHY0_DPTX 328 710f35f6225SXing Zheng #define SRST_P_UPHY0_APB 330 711f35f6225SXing Zheng #define SRST_P_UPHY0_TCPHY 332 712f35f6225SXing Zheng #define SRST_P_UPHY1_TCPHY 333 713f35f6225SXing Zheng #define SRST_P_UPHY0_TCPDCTRL 334 714f35f6225SXing Zheng #define SRST_P_UPHY1_TCPDCTRL 335 715f35f6225SXing Zheng 716f35f6225SXing Zheng /* pmu soft-reset indices */ 717f35f6225SXing Zheng 718f35f6225SXing Zheng /* pmu_cru_softrst_con0 */ 719f35f6225SXing Zheng #define SRST_P_NOC 0 720f35f6225SXing Zheng #define SRST_P_INTMEM 1 721f35f6225SXing Zheng #define SRST_H_CM0S 2 722f35f6225SXing Zheng #define SRST_H_CM0S_NOC 3 723f35f6225SXing Zheng #define SRST_DBG_CM0S 4 724f35f6225SXing Zheng #define SRST_PO_CM0S 5 725f35f6225SXing Zheng #define SRST_P_SPI6 6 726f35f6225SXing Zheng #define SRST_SPI6 7 727f35f6225SXing Zheng #define SRST_P_TIMER_0_1 8 728f35f6225SXing Zheng #define SRST_P_TIMER_0 9 729f35f6225SXing Zheng #define SRST_P_TIMER_1 10 730f35f6225SXing Zheng #define SRST_P_UART4 11 731f35f6225SXing Zheng #define SRST_UART4 12 732f35f6225SXing Zheng #define SRST_P_WDT 13 733f35f6225SXing Zheng 734f35f6225SXing Zheng /* pmu_cru_softrst_con1 */ 735f35f6225SXing Zheng #define SRST_P_I2C6 16 736f35f6225SXing Zheng #define SRST_P_I2C7 17 737f35f6225SXing Zheng #define SRST_P_I2C8 18 738f35f6225SXing Zheng #define SRST_P_MAILBOX 19 739f35f6225SXing Zheng #define SRST_P_RKPWM 20 740f35f6225SXing Zheng #define SRST_P_PMUGRF 21 741f35f6225SXing Zheng #define SRST_P_SGRF 22 742f35f6225SXing Zheng #define SRST_P_GPIO0 23 743f35f6225SXing Zheng #define SRST_P_GPIO1 24 744f35f6225SXing Zheng #define SRST_P_CRU 25 745f35f6225SXing Zheng #define SRST_P_INTR 26 746f35f6225SXing Zheng #define SRST_PVTM 27 747f35f6225SXing Zheng #define SRST_I2C6 28 748f35f6225SXing Zheng #define SRST_I2C7 29 749f35f6225SXing Zheng #define SRST_I2C8 30 750f35f6225SXing Zheng 751f35f6225SXing Zheng #endif 752